Semiconductor memory device

A semiconductor memory device, comprising:

• a clock inputting unit configured to receive a system clock and a data clock;
• a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal;
• a phase detecting unit configured to detect a phase difference between the data division clock and the system clock, and generate a detection signal corresponding to a result of the detection;
• a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences with each other in response to the data division clock;
• a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks;
• and
• a signal transmitting unit configured to selectively transmit an output signal of the data serializing unit or the detection signal to the outside in response to a training operation mode signal.

An operation method of a semiconductor memory device, the operation method comprising:

• receiving a system clock and a data clock;
• dividing a frequency of the data clock to generate a data division clock, wherein a phase of the data division clock is determined in response to an inversion division control signal;
• sensing an entry of a normal training mode or an entry of an auto training mode;
• generating a plurality of multiple phase data division clocks having respective predetermined phase differences with each other in response to the data division clock when the auto training mode is entered as a result of the sense;
• serializing predetermined parallel pattern data in correspondence with the respective multiple phase data division clocks;
• and
• transmitting the serialized pattern data to the outside.