US 7,889,593 B2 · Method and apparatus for generating a sequence of clock signals

Abstract

A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch.

Claims22

Dependent claims

A command latch operable to latch command data using a command clock signal, where the command data and the command clock signal are delayed relative to each other, the command latch comprising:

a latch circuit configured to receive the command data and receive a selected internal clock signal appropriate to latch the command data, the latch circuit operable to latch the command data in accordance with the selected internal clock signal;
a clock generator configured to receive a master clock signal based on the command clock signal, the clock generator operable to generate a plurality of internal clock signals, including the selected internal clock signal and a reference clock signal, each internal clock signal having a different phase relative to the command clock signal and the reference clock signal having a phase relative to the command clock signal, the clock generator further configured to receive a select signal, the clock generator operable to couple the selected internal clock signal to the latch circuit responsive to the select signal wherein the clock generator comprises:
a first locked loop operable to lock the phase between a first one of the plurality of internal clock signals and the reference clock signal;
and a second locked loop operable to lock the phase between the master clock signal and the reference clock signal;
a select circuit coupled to the latch circuit and the clock generator, the select circuit operable to identify the selected internal clock signal from the plurality of internal clock signals and generate the select signal for the clock generator.

2 more elements

A command data latch circuit for storing a command data packet at a time determined from a command clock signal, the command data latch comprising:

a latch circuit having a data input and a clock input, the data input adapted to receive the command data packet and the latch circuit operable to store the command data packet responsive to a clock signal applied to the clock input;
a clock generator circuit operable to generate a sequence of clock signals from a periodic master clock signal, the sequence of clock signals increasingly delayed from a first clock signal to a last clock signal, the sequence of clock signals including the clock signal applied to the clock input of the latch circuit, wherein the clock generator comprises:
a first locked loop operable to generate the sequence of clock signals and lock two of the clock signals in the sequence such that they have a predetermined phase with respect to each other;
and a second locked loop operable to lock one of the clock signals in the sequence of clock signals to the master clock signal so that the clock signals in the sequence have respective phases with respect to the master clock signal;
and
a select circuit operable to determine which of the signals in the sequence of clock signals from the clock generator should be used to cause the latch circuit to store the command data packet and generate the select signal corresponding thereto.

3 more elements

A command latch circuit operable to latch command data using a command clock, wherein the command data and the command clock have a delay relative to each other, the command latch circuit comprising:

a clock generator configured to receive the command clock, the clock generator operable to generate a plurality of internal clock signals such that each of the plurality of internal clock signals has a predetermined phase relative to the phase of the command clock wherein the clock generator comprises:
an inner locked loop operable to generate a sequence of signals having increasing predetermined phases relative to one another;
and an outer locked loop operable to align one of the sequence of signals to the command clock signal, thereby generating the sequence of internal clock signals such that each of the internal clock signals has a different predetermined phase relative to the command clock signal;
a latch circuit configured to receive the command data and a selected clock signal of the sequence of internal clock signals, the latch circuit operable to latch the command data using the selected clock signal;
and
a select circuit coupled to the clock generator and the latch circuit, the select circuit operable to determine the selected clock signal of the sequence of clock signals that will properly latch the command data.

3 more elements

Dependencies are inferred from the claim text.

Method and apparatus for generating a sequence of clock signals

Life of this patent

Method and apparatus for generating a sequence of clock signals

Life of this patent

Abstract

Claims22