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US 7,889,589 B2Granted
Memory including periphery circuitry to support a portion or all of the multiple banks of memory cells
AssigneeQimonda AG
InventorsSteffen Loeffler, Wolfgang Hokenmaier
Life of this patent
Estimating the term…
Abstract
A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells.
Claims25
A memory comprising:
- a plurality of memory cell banks;
- periphery circuitry configured to support a maximum number of memory cell banks which is equal to or greater than the plurality of memory cell banks and comprising:
- switches that are set to put the periphery circuitry into a first mode to support the plurality of memory cell banks when the plurality of memory cell banks total fewer than the maximum number of memory cell banks and a second mode to support the plurality of memory cell banks when the plurality of memory cell banks total the maximum number of memory cell banks.
An integrated circuit comprising:
- a first bank of memory cells;
- a second bank of memory cells;
- and
- periphery circuitry configured to support a maximum number of memory cell banks which is more than two banks of memory cells, wherein the periphery circuitry includes switches that are set to put the periphery circuitry into a first mode for supporting only the first bank of memory cells and the second bank of memory cells and set to put the periphery circuitry into a second mode for supporting the maximum number of memory cell banks.
1 more element
A memory comprising:
- a plurality of memory cell banks;
- means for supporting a maximum number of memory cell banks which is equal to or greater than the plurality of memory cell banks;
- and
- means for setting the means for supporting into a first mode to support the plurality of memory cell banks when the plurality of memory cell banks total fewer than the maximum number of memory cell banks and into a second mode to support the plurality of memory cell banks when the plurality of memory cell banks total the maximum number of memory cell banks.
1 more element
A method of operating a memory including a plurality of memory cell banks, comprising:
- supporting the plurality of memory cell banks via periphery circuitry configured to support a maximum number of memory cell banks which is equal to or greater than the plurality of memory cell banks;
- and
- setting switches to put the periphery circuitry into one of a first mode to support the plurality of memory cell banks when the plurality of memory cell banks total fewer than the maximum number of memory cell banks and a second mode to support the plurality of memory cell banks when the plurality of memory cell banks total the maximum number of memory cell banks.
A method of operating a memory including a first bank of memory cells and a second bank of memory cells, the method comprising:
- supporting the first bank of memory cells and the second bank of memory cells via periphery circuitry configured to support a maximum number of memory cell banks which is more than two banks of memory cells;
- and
- setting switches that put the periphery circuitry into one of a first mode for supporting only the first bank of memory cells and the second bank of memory cells and a second mode for supporting the maximum number of memory cell banks.
Dependencies are inferred from the claim text.