Balancing a signal margin of a resistance based memory circuit

A circuit comprising:

• a first transistor load of a data cell;
• a bit line coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure, wherein during a read operation the bit line has a first voltage value when the MTJ structure has a first logic state and a second voltage value when the MTJ structure has a second logic state;
• and
• a second transistor load of a reference cell, the second transistor load coupled to the first transistor load, the second transistor load having an associated reference voltage value;
• wherein a characteristic of the first transistor load is adjustable to modify the first voltage value and the second voltage value, but without substantially changing the reference voltage value.

A circuit comprising:

• a first transistor load of a data cell;
• a bit line coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure, the bit line adapted to detect data having a logic one value when the bit line has a first voltage value, the bit line further adapted to detect data having a logic zero value when the bit line has a second voltage value;
• and
• a second transistor load of a reference cell, the second transistor load coupled to the first transistor load, the second transistor load having an associated reference voltage value;
• wherein the first transistor load includes at least one source degeneration transistor.