Semiconductor memory device having input first-stage circuit

A memory module comprising:

• a circuit board;
• a wiring layer formed on the circuit board to convey a DC voltage;
• and
• a plurality of semiconductor devices mounted on the circuit board, each of the semiconductor devices comprising, on a single semiconductor chip;
• a plurality of DQ terminals each receiving a DQ signal supplied from outside of the single semiconductor device,
• a plurality of input circuits each including a first input node coupled to a corresponding one of the DQ terminals to receive the DQ signal and a second input node supplied with a reference voltage, and comparing the DQ signal with the reference voltage to produce an output signal at an output node thereof,
• a second terminal, and
• a low-pass filter coupled at one end thereof to the second terminal and at the other end thereof in common to the second input nodes of the input circuits;
• the second terminals of the semiconductor devices being connected in common to the wiring layer to receive the DC voltage,
• each of the low-pass filters of the semiconductor devices transmitting the DC voltage from the second terminal of an associated one of the semiconductor devices to the second input nodes of the input circuits of the associated one of the semiconductor devices as the reference voltage and attenuating a noise signal which may be supplied to the second terminals together with the DC voltage from outside of the associated one of the semiconductor devices so that a difference between the reference voltage and the DC voltage caused by the noise signal is suppressed.

A system comprising:

• a generator generating a DC voltage;
• and
• a memory module comprising;
• a circuit board;
• a wiring layer formed on the circuit board to convey the DC voltage;
• and
• a plurality of semiconductor devices mounted on the circuit board, each of the semiconductor devices comprising, on a single semiconductor chip;
• a plurality of DQ terminals each receiving a DQ signal supplied from outside of the single semiconductor device,
• a plurality of input circuits each including a first input node coupled to a corresponding one of the DQ terminals to receive the DQ signal and a second input node supplied with a reference voltage, and comparing the DQ signal with the reference voltage to produce an output signal at an output node thereof,
• a second terminal, and
• a low-pass filter coupled at one end thereof to the second terminal and at the other end thereof in common to the second input nodes of the input circuits;
• the second terminals of the semiconductor devices being connected in common to the wiring layer to receive the DC voltage,
• each of the low-pass filters of the semiconductor devices transmitting the DC voltage from the second terminal of an associated one of the semiconductor devices to the second input nodes of the input circuits of the associated one of the semiconductor devices as the reference voltage and attenuating a noise signal which may be supplied to the second terminals together with the DC voltage from outside of the associated one of the semiconductor devices so that a difference between the reference voltage and the DC voltage caused by the noise signal is suppressed.