Memory circuit and tracking circuit thereof
AssigneeMediatek Inc.
InventorChia Wei Wang
Life of this patent
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Abstract
A tracking circuit of a memory circuit is provided. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells and a dummy bit line. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for lowering down a dummy bit line signal on the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled to the dummy cells and carries the dummy bit line signal.
Claims21
A tracking circuit of a memory circuit, coupled between a control circuit and a sense amplifier, delaying a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect a data bit output by a memory cell array, comprising:
- a plurality of dummy cells, at least one of the plurality of dummy cells comprising a plurality of cascaded transistors cascaded between a dummy bit line and a ground voltage for lowering a dummy bit line signal on the dummy bit line when the word-line pulse signal is enabled;
- and
- the dummy bit line, coupled to the dummy cells, carrying the dummy bit line signal.
A memory circuit, comprising:
- a control circuit, enabling a word-line pulse signal to initiate reading of a memory cell array;
- a word-line driver, enabling a word line according to the word-line pulse signal to trigger the memory cell array;
- the memory cell array, reading a data bit from a memory cell directed by the enabled word line and outputting the data bit onto a bit line;
- a tracking circuit, delaying the word-line pulse signal by a delay period to generate a sense amplifier enable signal;
- and
- a sense amplifier, detecting the data bit on the bit line to generate an output signal when the sense amplifier enable signal is enabled,
- wherein the tracking circuit comprises a plurality of dummy cells and a dummy bit line coupled to the dummy cells, the dummy bit line carrying a dummy bit line signal, at least one of the dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for lowering the dummy bit line signal on the dummy bit line when the word-line pulse signal is enabled.
Dependencies are inferred from the claim text.