Digital DLL circuit
AssigneeFujitsu Semiconductor Limited
InventorShinji Wakasa
Life of this patent
Estimating the term…
Abstract
A digital delay locked loop circuit generates a delay value to delay the timing of taking in read-data by a memory interface when data is read from a memory. The digital delay locked loop circuit includes a selector that selects either one of a clock signal and a data strobe signal as a signal to output; a delay line that induces delay on the signal output from the selector when the signal passes through the delay line; and a phase-comparing/delay-value determining unit that compares a phase of the clock signal and a phase of the signal output from the delay line, and that determines a delay value that defines an amount of delay to be induced on the data strobe signal when passing through the delay line.
Claims11
A digital delay locked loop circuit that generates a delay value to delay timing of taking in read-data by a memory interface when data is read from a memory, the digital delay locked loop circuit comprising:
- a selector that selects either one of a clock signal and a data strobe signal as a signal to output;
- a delay line that induces delay on the signal output from the selector when the signal passes through the delay line;
- and
- a phase-comparing/delay-value determining unit that compares a phase of the clock signal and a phase of the signal output from the delay line, and that determines a delay value that defines an amount of delay to be induced on the data strobe signal when passing through the delay line, wherein
- the clock signal has a frequency twice as high as, or higher than a clock signal input to the memory.
Dependencies are inferred from the claim text.