US 7,889,579 B2Granted

Using differential data strobes in non-differential mode to enhance data capture window

AssigneeProMOS Technologies Pte. Ltd.

InventorJon Allan Faue

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Abstract

A data capture circuit includes strobes that track input data even when conditions arise that cause the differences in skew from interpreting data state ones and zeros. This is accomplished whether these skews arise from reference voltage variation, data pattern loading, power supply droop, process variations within the chip itself, or other causes. The differential input strobes of the data capture circuit are input into individual input buffers, each compared against a reference voltage individually, as well as a data input pin. The outputs from these buffers are maintained separate from each other all the way to the point where the input data is latched. In latching the input data, data ones are latched entirely based on input signals derived from a rising edge (both strobes and data), and zeros are latched entirely based on input signals derived from a falling edge (both strobes and data).

Claims10

Dependent claims

A data capture circuit comprising:

a differential strobe signal including first and second single-ended strobe signals;
a single-ended data signal;
a reference voltage;
a first differential amplifier having a first input for receiving the first single-ended strobe signal, a second input for receiving the reference voltage, and an output;
a second differential amplifier having a first input for receiving the single-ended data signal, a second input for receiving the reference voltage, and an output;
a third differential amplifier having a first input for receiving the second single-ended strobe signal, a second input for receiving the reference voltage, and an output;
a first dual-cascode circuit having first and second P-channel transistors and first and second N-channel transistors with their respective current paths in cascode connection, a gate of the first P-channel transistor being coupled to the output of the first differential amplifier, a gate of the second P-channel transistor and the first N-channel transistor being coupled together and to the output of the second differential amplifier, and a gate of the second N-channel transistor being coupled to the output of the third differential amplifier, and an output for providing a rising data signal;
and
a second dual-cascode circuit having first and second P-channel transistors and first and second N-channel transistors with their respective current paths in cascade connection, a gate of the first P-channel transistor being coupled to the output of the first differential amplifier, a gate of the second P-channel transistor and the first N-channel transistor being coupled together and to the output of the second differential amplifier, and a gate of the second N-channel transistor being coupled to the output of the third differential amplifier, and an output for providing a falling data signal,
wherein the rising and falling data signals are subsequently processed to provide falling edge zero, falling edge one, rising edge zero, and rising edge one data signals.

7 more elements

A data capture circuit comprising:

a differential strobe signal including first and second single-ended strobe signals;
a single-ended data signal;
a reference voltage;
a first differential amplifier having a first input for receiving the first single-ended strobe signal, a second input for receiving the reference voltage, and an output;
a second differential amplifier having a first input for receiving the single-ended data signal, a second input for receiving the reference voltage, and an output;
a third differential amplifier having a first input for receiving the second single-ended strobe signal, a second input for receiving the reference voltage, and an output;
a first dual-cascade circuit having first and second P-channel transistors and first and second N-channel transistors with their respective current paths in cascode connection, a gate of the first P-channel transistor being coupled to the output of the first differential amplifier, a gate of the second P-channel transistor and the first N-channel transistor being coupled together and to the output of the second differential amplifier, and a gate of the second N-channel transistor being coupled to the output of the third differential amplifier, and an output for providing a rising data signal;
and
a second dual-cascode circuit having first and second P-channel transistors and first and second N-channel transistors with their respective current paths in cascade connection, a gate of the first P-channel transistor being coupled to the output of the first differential amplifier, a gate of the second P-channel transistor and the first N-channel transistor being coupled together and to the output of the second differential amplifier, and a gate of the second N-channel transistor being coupled to the output of the third differential amplifier, and an output for providing a falling data signal,
wherein the rising and falling data signals are subsequently processed to provide captured data signals such that an initial setup time period between at least one of the strobe signals and the data signal is maintained during subsequent processing.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/021,209Filed 28 Jan 2008
Published: US 2009/0190410 A130 Jul 2009
Granted: 15 Feb 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 7/1078
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data input circuits, e.g. write amplifiers, data…
G11C 7/1087
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input latches
G11C 7/1093
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: input synchronization
H03K 5/08
Shaping pulses: by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding