Single-strobe operation of memory devices
AssigneeMosaid Technologies Incorporated
InventorsRoland Schuetz, Jin-Ki Kim
Life of this patent
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Abstract
An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
Claims20
A memory device comprising:
- an internal memory device including:
- a plurality of data bus inputs for receiving a signal on a data bus;
- a first strobe input for receiving a first strobe signal indicating that said signal on said data bus relates to a first type of packet;
- and
- a second strobe input for receiving a second strobe signal indicating that said signal on said data bus relates to a second type of packet;
- and
- a packet header decoder including:
- a data bus input for receiving a portion of said signal on said data bus;
- a third strobe input for receiving a third strobe signal;
- a pulse generator for generating a fourth strobe signal based, at least in part, on said third strobe signal;
- and
- a strobe generator for generating one of said first strobe signal and said second strobe signal based, at least in part, on:
- said portion of said signal on said data bus;
- and
- said fourth strobe signal.
A memory arrangement comprising:
- a memory controller including:
- a strobe output for transmitting a third strobe signal delimiting a primary packet;
- and
- a plurality of data bus outputs for transmitting said primary packet on a data bus, said primary packet including a packet header followed by a payload, said packet header indicating a type to be associated with said payload;
- and
- a memory device comprising:
- an internal memory device including:
- a plurality of data bus inputs for receiving said primary packet on said data bus;
- a first strobe input for receiving a first strobe signal indicating that said signal on said data bus relates to a first type of packet;
- and
- a second strobe input for receiving a second strobe signal indicating that said signal on said data bus relates to a second type of packet;
- and
- a packet header decoder including:
- a data bus input for receiving a portion of said primary packet on said data bus;
- a third strobe input for receiving said third strobe signal;
- a pulse generator for generating a fourth strobe signal based, at least in part, on said third strobe signal;
- and
- a strobe generator for generating one of said first strobe signal and said second strobe signal based, at least in part, on:
- said portion of said primary packet on said data bus;
- and
- said fourth strobe signal.
Dependencies are inferred from the claim text.