Semiconductor storage device
AssigneeFujitsu Limited
InventorHirotoshi Sasaki
Life of this patent
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Abstract
This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit in which input and output terminals of a pair of inverters are cross-connected and which maintains complementary levels at a pair of storage nodes, and a pair of write transistors provided between the pair of storage nodes and a prescribed power supply voltage. Further, the gate potentials of the pair of write transistors are respectively controlled according to a row address, a column address, and write data.
Claims16
A static random access memory, comprising:
- a plurality of memory cells arranged in row and column directions,
- wherein the plurality of memory cells each have:
- a latch circuit, in which input and output terminals of a pair of inverters are cross-connected, and which maintains complementary levels at a pair of storage nodes;
- and
- a pair of write transistors, provided between the pair of storage nodes and a prescribed power supply voltage;
- and wherein the gate potentials of the pair of write transistors are respectively controlled according to a row address, a column address, and write data.
A static random access memory, comprising:
- a plurality of memory cells, arranged in row and column directions;
- a plurality of first write word lines, extending in a first direction among the row and column directions;
- and
- a plurality of second write word line pairs, extending in a second direction among the row and column directions;
- wherein the plurality of memory cells each have a latch circuit, in which input and output terminals of a pair of inverters are cross-connected and which maintains complementary levels at a pair of storage nodes, a pair of write transistors provided between the pair of storage nodes and a prescribed power supply voltage, and a pair of write selection transistors which are provided between the first write word line and the gates of the pair of write transistors, and the gates of which are controlled by the second write word line pair,
- and wherein the gate potentials of the pair of write transistors are respectively controlled according to the potentials of the first write word line and of the second write word line pair.
Dependencies are inferred from the claim text.