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US 7,889,574 B2Granted
Semiconductor memory device employing clamp for preventing latch up
AssigneeHynix Semiconductor Inc.
InventorsSang-Jin Byeon, Kang-Seol Lee
Life of this patent
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Abstract
A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.
Claims10
A semiconductor memory device, comprising:
- a pair of data lines;
- a first driving unit comprising a first CMOS transistor, configured to drive an input signal to one of the pair of data lines;
- a second driving unit comprising a second CMOS transistor, configured to drive an input signal to the other data line;
- a precharging/equalizing unit comprising at least two MOS transistors, configured to precharge and equalize the pair of data lines;
- a first clamping unit configured to supply a source voltage of the first CMOS transistor in response to a bulk bias voltage of the first CMOS transistor;
- a second clamping unit configured to supply a source voltage of the second CMOS transistor in response to a bulk bias voltage of the second CMOS transistor;
- and
- a third clamping unit configured to supply a source voltage of the two MOS transistors in response to a bulk bias voltage of the two MOS transistor.
5 more elements
A semiconductor memory device, comprising:
- a CMOS transistor configured to includes a PMOS transistor and an NMOS transistor;
- and
- a clamping unit configured to supply a source voltage of the CMOS transistor in response to a bulk bias voltage of the CMOS transistor,
- wherein the PMOS transistor and the NMOS transistor have gates commonly forming an input node and drains commonly forming an output node of the CMOS transistor, the PMOS transistor uses a boosted voltage as a bulk bias, and the NMOS transistor uses a reduced voltage as a bulk bias.
1 more element
Dependencies are inferred from the claim text.