Memory with high reading performance and reading method thereof
AssigneeMacronix International Co., Ltd.
InventorsWen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
Life of this patent
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Abstract
A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.
Claims16
A memory, comprising:
- a plurality of memory regions each comprising:
- a target memory cell;
- a source line coupled to a first terminal of the target memory cell;
- a bit line coupled to a second terminal of the target memory cell;
- a reading control circuit for selectively applying a working voltage to the source line;
- a clamp transistor having a first terminal coupled to the bit line;
- a latch coupled to a second terminal of the clamp transistor;
- a select transistor for selecting the bit line, wherein a second terminal of the select transistor is coupled to the first terminal of the clamp transistor;
- a pre-charge transistor having a first terminal for receiving the working voltage, and a second terminal coupled to the second terminal of the clamp transistor;
- a select switch having a first terminal coupled to the second terminal of the clamp transistor, and a second terminal coupled to the latch;
- and
- a reset switch having a first terminal coupled to the second terminal of the clamp transistor, and a second terminal for receiving a ground voltage.
A memory reading method for reading a memory, which comprises a plurality of memory regions each comprising a target memory cell, a source line coupled to a first terminal of the target memory cell, a bit line coupled to a second terminal of the target memory cell and a sensing node, a clamp transistor having a first terminal coupled to the bit line, a latch coupled to a second terminal of the clamp transistor, a select transistor for selecting the bit line and having a second terminal coupled to the first terminal of the clamp transistor, a pre-charge transistor having a first terminal for receiving the working voltage, and a second terminal coupled to the second terminal of the transistor, a select switch having a first terminal coupled to the second terminal of the clamp transistor, and a second terminal coupled to the latch, and a reset switch having a first terminal coupled to the second terminal of the clamp transistor, and a second terminal for receiving a ground voltage, the memory reading method comprising the steps of:
- discharging the bit line to the ground voltage and turning on the reset switch in a discharge period such that the voltage level of the second terminal of the clamp transistor is the ground voltage;
- charging up the sensing node;
- applying a working voltage to the source line;
- and
- sensing the sensing node.
Dependencies are inferred from the claim text.