Memory device input buffer, related memory device, controller and system
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-woo Lee, Jung-yong Choi, Jong-hyun Choi
Life of this patent
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Abstract
Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the input buffer is enabled only when the second signal shows a non-power down mode and the first signal shows a chip selection state. The input buffer is at least one selected from the group consisting of a row address strobe input buffer, a column address strobe input buffer, and an address input buffer.
Claims22
An input buffer for a memory device, the input buffer being configured to receive a chip selection signal indicating either a chip selection state or a non-chip selection state, and a power down signal indicating either a power down mode or a non-power down mode of operation for the memory device, wherein the input buffer is enabled and disabled in response to the chip selection signal and the power down signal indicative of power down information.
A memory device, comprising:
- a clock buffer configured adapted to receive a clock signal having periodically occurring first and second CLK signal type transitions;
- a first input buffer configured to receive a chip selection signal and having a setup time and hold time defined in relation to a first CLK signal type transition occurring at a first time;
- and
- at least one second input buffer configured to receive at least an input signal, other than the chip selection signal, and having a setup time and hold time defined in relation to a second CLK signal type transition occurring at a second time.
A memory controller, comprising:
- circuitry configured to generate a clock signal having periodically occurring first and second CLK signal type transitions;
- circuitry configured to generate a chip selection signal having a setup time and hold time defined in relation to a first CLK signal type transition occurring at a first time;
- and
- circuitry configured to generate at least one input signal, other than the chip selection signal, and having a setup time and hold time defined in relation to a second CLK signal type transition occurring at a second time.
A memory system, comprising:
- a memory controller configured to generate predetermined input signals in relation to a clock signal, the clock signal having periodically occurring first and second CLK signal type transitions;
- and
- a memory configured to perform memory operations in response to the input signals, wherein the input signals comprise a chip selection signal having a setup time and hold time defined in relation to a first CLK signal type transition occurring at a first time, and at least one other input signal having a setup time and hold time defined in relation to a second CLK signal type transition occurring at a second time.
Dependencies are inferred from the claim text.