Memory, memory operating method, and memory system
AssigneeFujitsu Semiconductor Limited
InventorKeisuke Watanabe
Life of this patent
Estimating the term…
Abstract
A memory includes a plurality of memory cells each of which includes a memory transistor and a selection transistor; a control gate line; a selection gate line; a source line; a bit line; a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation; a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage; and a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed.
Claims9
A memory comprising:
- a plurality of memory cells each of which includes a memory transistor and a selection transistor coupled to the memory transistor;
- a control gate line commonly coupled to gates of the memory transistors;
- a selection gate line commonly coupled to gates of the selection transistors;
- a source line commonly coupled to the memory cells;
- a bit line coupled to each of the memory cells;
- a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation of the memory cell;
- a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage;
- and
- a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed.
A memory operating method comprising:
- setting, in a program operation of a memory that includes a plurality of memory cells each of which includes a memory transistor and a selection transistor coupled to the memory transistor, a control gate line commonly coupled to gates of the memory transistors, a selection gate line commonly coupled to gates of the selection transistors, a source line commonly coupled to the memory cells, and a bit line coupled to each of the memory cells, the control gate line and the selection gate line at a first voltage;
- setting the source line at a second voltage;
- setting the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage;
- and
- setting the bit line at a fourth voltage after the source line is set at the second voltage, wherein the bit line is coupled to a memory cell being programmed.
A memory system comprising:
- a memory;
- and
- a controller that accesses the memory,
- wherein the memory includes:
- a plurality of memory cells each of which includes a memory transistor and a selection transistor coupled to the memory transistor;
- a control gate line commonly coupled to gates of the memory transistors;
- a selection gate line commonly coupled to gates of the selection transistors;
- a source line commonly coupled to the memory cells;
- a bit line coupled to each of the memory cells;
- a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation of the memory cell;
- a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage;
- and
- a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed.
Dependencies are inferred from the claim text.