Nonvolatile semiconductor memory device in which an amount of data to be stored in a memory cell is allocated to every other word line units of one word line

A nonvolatile semiconductor memory device comprising:

• a plurality of word lines having odd word lines and even word lines;
• a plurality of bit lines;
• a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively;
• and
• a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each memory cell of said plurality of memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, at the time of programming , the number of said storage states of said memory cells connected to said odd word lines is different from the number of said storage states of said memory cells connected to said even word lines, and the number of said storage states being different in two of said memory cells, one of said two memory cells being arranged in the middle of a series of three memory cells of said plurality of memory cells connected in series to the same bit line, and the other memory cell of said two memory cells being adjacent to the middle memory cell.

A nonvolatile semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of sense amplifiers, each amplifier being connected to one of said plurality of bit lines respectively;
• and
• a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each memory cell of said plurality of memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of said plurality of word lines respectively, said plurality of memory strings being connected to a corresponding bit line of said plurality of bit lines respectively, each of first addresses being allocated to one of said plurality of said memory cells, each of second addresses being allocated to two of said plurality of memory cells which are adjacent on the same bit line, said two of said plurality of memory cells being selected by a corresponding first address of said first addresses and a corresponding second address of said second addresses, and at the time of programming , the number of said storage states being different in two of said memory cells, one of said two memory cells being arranged in the middle of a series of three memory cells of said plurality of memory cells connected in series to the same bit line, and the other memory cell of said two memory cells being adjacent to the middle memory cell.