Single-poly non-volatile memory cell
AssigneeNovelics, LLC
InventorsEsin Terzioglu, Gil I. Winograd, Morteza Cyrus Afghahi
Life of this patent
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Abstract
A non-volatile memory cell includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate.
Claims6
A non-volatile memory cell, comprising:
- a substrate including diffusion regions for a read-out transistor;
- a capacitor formed in a polysilicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate;
- and
- a programming line coupled to the control gate, wherein the substrate is p− doped such that the read-out transistor is an NMOS transistor, the substrate including an n-well adjacent the interdigitation of the finger extensions, the n-well having an active region with a first portion doped n+ and a second portion doped p+, the floating gate including an additional extension that overlays both portions in the active region so as to create an n+ doped channel and a p+ doped channel in the active region.
A method of programming a non-volatile memory cell, wherein the non-volatile memory cell includes a fringe capacitor formed in a single polysilicon layer, the fringe capacitor forming a floating gate and a control gate that capacitively couple through interdigitated fingers, the control gate coupling to a programming line and the floating gate coupling to an erase line through a tunneling device, the method comprising:
- charging the programming line to a programming voltage;
- and
- while the programming line is charged, lowering a potential of the erase line such that electrons tunnel from the erase line into the floating gate so as to program the non-volatile memory cell, wherein the floating gate forms a gate for a read-out transistor, the method further comprising:
- lowering a potential of a terminal for the read-out transistor while the programming line is charged such that electrons tunnel through the gate of the read-out transistor into the floating gate.
Dependencies are inferred from the claim text.