Apparatus and method of nonvolatile memory device having three-level nonvolatile memory cells

An operating method of a nonvolatile memory device, comprising:

• providing a plurality of nonvolatile memory cells, each of said memory cells storing one among first data through third data corresponding to first through third resistance levels, respectively, each of said resistance levels different from one another where first resistance level is the lowest level and the third resistance level is the highest level among the three resistance levels;
• setting a cell type of each of the plurality of nonvolatile memory cells as a 3-level memory cell;
• writing first data in one nonvolatile memory cell selected from the memory cell array and writing third data in another nonvolatile memory cell selected from the memory cell array during a first interval of the write operation.

A nonvolatile memory device comprising:

• a memory cell array having first through third nonvolatile memory cells, each of said memory cells capable of storing one among first data through third data corresponding to first through third resistance levels, respectively, wherein the first resistance level is a lowest of the first through third resistance levels and the third resistance level is a highest of the first through third resistance levels;
• and
• a write circuit connected to said memory cell array and configured to write the first data and the third data in the first and third nonvolatile memory cells, respectively, during a first interval of a write operation, said write circuit further configured to write the second data in the second nonvolatile memory cell during a second interval of the write operation.

A nonvolatile memory device comprising:

• a memory cell array having a plurality of nonvolatile memory cells, each of said memory cells capable of storing one among first data through third data corresponding to first through third resistance levels, respectively, each of said resistance levels being different from one another, the first resistance level being the lowest resistance level and the third resistance level being the highest resistance level among the three resistance levels;
• and
• a read circuit connected to said array and configured to read internal data stored in the plurality of nonvolatile memory cells, the read circuit configured to supply a first read current to the nonvolatile memory cell to be read to determine whether the internal data stored in the nonvolatile memory cell is first internal data, said read circuit configured to supply a second read current to the nonvolatile memory cell to be read to determine whether the internal data stored in the nonvolatile memory cell is third internal data.