2T SRAM cell structure
AssigneeFaraday Technology Corp.
InventorsWei-Chiang Shih, Chen-Hao Po, Kwo-Jen Liu
Life of this patent
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Abstract
A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.
Claims19
A SRAM cell structure comprising:
- a first N type switch having a control terminal connected to a word line and a first terminal connected to a bit line;
- a second N type switch having a control terminal connected to the word line and a first terminal connected to an inverted bit line;
- a first storage node having a first terminal connected to a second terminal of the first N type switch and a floating second terminal;
- and
- a second storage node having a first terminal connected to a second terminal of the second N type switch and a floating second terminal.
A static random access memory comprising:
- a main control circuit for receiving multiple address signals, a clock signal and a read/write signal, wherein the address signals includes column address signals and row address signals;
- a column decoder connected to the main control circuit, wherein the column address signals are transmitted to the column decoder for controlling a bit line;
- a row decoder connected to the main control circuit, wherein the row address signals are transmitted to the row decoder for controlling a word line;
- a memory cell array connected to the column decoder and the row decoder;
- a sense amplifier and input/output control circuit connected to the memory cell array;
- and
- a hidden refresh unit connected to the main control circuit, wherein when the static random access memory is in a normal operation without refresh mode, the hidden refresh unit performs only a normal write/read operation within one clock cycle, and when the static random access memory is in a normal operation with refresh mode, the hidden refresh unit performs a write/read operation followed by a refresh operation on the memory cell array within one clock cycle.
Dependencies are inferred from the claim text.