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US 7,889,538 B2Granted
Three-dimensional memory device
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
Estimating the term…
Abstract
A three-dimensional memory device includes: a plurality of mats laminated therein, each having memory cells arranged in a two-dimensional manner; and access signal lines and data lines to select memory cells in each mat being shared between respective adjacent mats. Laminated mats are divided into three or more groups. When selecting one of these groups, memory cells in some of the remaining groups are biased so that a leakage current flows therethrough, while memory cells in the rest of the remaining groups are biased so that a leakage current does not flow therethrough.
Claims19
A three-dimensional memory device comprising:
- a plurality of mats laminated therein, each having memory cells arranged in a two-dimensional manner;
- and access signal lines and data lines to select memory cells in each mat being shared between respective adjacent mats,
- laminated mats being divided into three or more groups, and, when selecting one of these groups, memory cells in some of the remaining groups being biased so that a leakage current flows there through, while memory cells in the rest of the remaining groups being biased so that a leakage current is reduced,
- wherein each of the mats includes memory cells positioned at cross-points of the access signal lines and the data lines, each of the memory cells having a variable resistance element and a diode connected in series, the variable resistance element being capable of setting a resistance value in a reversible manner by applying voltage, and diodes between the access signal lines and the data lines are set to reverse-biased state in the some of the remaining groups, while diodes between access signal lines and data lines are set to substantially-zero-biased state in the rest of the remaining groups.
1 more element
A three-dimensional memory device comprising:
- a semiconductor substrate;
- a three-dimensional cell array having a plurality of mats laminated on the semiconductor substrate, each having memory cells arranged in a two-dimensional manner, and access signal lines and data lines to select memory cells in each mat being shared between respective adjacent mats;
- and
- a control circuit formed on the semiconductor substrate below the three-dimensional cell array, the control circuit controlling read and write of the three-dimensional cell array,
- the control circuit having a group selection circuit, the group selection circuit, when mats in the three-dimensional cell array being divided into three or more groups, and when one of these groups being selected, being configured to select some of the remaining groups concurrently, and not to select the rest of the remaining groups.
2 more elements
A three-dimensional memory device comprising:
- a semiconductor substrate;
- a mat including memory cells arranged in a two-dimensional manner on the semiconductor substrate, the memory cells positioned at cross-points of access signal lines and data lines, each of the memory cells having a variable resistance element and a diode connected in series, the variable resistance element being capable of setting a resistance value in a reversible manner by applying voltage;
- a three-dimensional cell array including a plurality of the mats laminated therein, with the access signal lines or the data lines being shared between adjacent mats;
- and
- a control circuit formed on the semiconductor substrate below the three-dimensional cell array, the control circuit controlling read and write of the three-dimensional cell array,
- the control circuit having a group selection circuit, the group selection circuit, when mats in the three-dimensional cell array being divided into three or more groups, and when one of these groups being selected, being configured to select some of the remaining groups concurrently, and not to select the rest of the remaining groups, and
- when selecting one of the plurality of groups in the three-dimensional cell array, the group selection circuit being configured to set diodes between access signal lines and data lines to reverse-biased state in some of the remaining groups, and memory cells to inactive state without any leakage in the rest of the remaining groups.
4 more elements
Dependencies are inferred from the claim text.