Back to results
US 7,889,536 B2Granted
Integrated circuit including quench devices
AssigneeQimonda AG
InventorsThomas Happ, Jan Boris Philipp
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.
Claims18
A memory comprising:
- a bit line;
- phase change memory cells coupled to the bit line;
- a circuit coupled to the bit line, the circuit configured to perform a reset operation of a memory cell;
- and
- at least two means for quenching a write signal on the bit line during a reset operation of a memory cell,
- wherein the means for quenching comprise at least two quench transistors directly connected to the bit line at different points along the bit line, each of the at least two quench transistors comprising a source-drain path coupled between the bit line and a common or ground,
- wherein each phase change memory cell comprises a selection transistor coupled to a phase change element, and
- wherein each selection transistor includes dimensions equal to dimensions of each quench transistor.
5 more elements
A method for programming a memory, the method comprising:
- selecting, via a circuit, a phase change memory cell to be reset;
- applying, via the circuit, a reset signal to a bit line coupled to the memory cell;
- and
- selecting, via the circuit, at least two quench transistors directly connected to the bit line at different points along the bit line to quench the reset signal to complete the resetting of the memory cell,
- wherein selecting the phase change memory cell comprises selecting an access transistor coupled to a phase change element, and
- wherein selecting the at least two quench transistors comprises selecting at least two quench transistors having dimensions equal to dimensions of the access transistor.
3 more elements
A memory comprising:
- a line;
- at least two quench devices directly connected to the line at different points along the line;
- a phase change memory cell coupled to the line;
- and
- a circuit coupled to the line, the circuit configured to perform a write operation of the memory cell,
- wherein the at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell, and
- wherein the quench devices are coupled to the line at a distance from one end of the line as defined by ½n, . . . , (2n−1)/2n, where “n” equals the number of quench devices.
4 more elements
A method for programming a memory, the method comprising:
- selecting, via a circuit, a phase change memory cell to be programmed;
- applying, via the circuit, a write signal to a line coupled to the selected memory cell;
- and
- selecting, via the circuit, at least two quench devices directly connected to the line at different points along the line to quench the write signal to complete the programming of the selected memory cell,
- wherein selecting the at least two quench devices comprises selecting an “n” number of quench devices coupled to the line at a distance from one end of the line as defined by ½n, . . . , (2n−1)/2n.
2 more elements
Dependencies are inferred from the claim text.