Back to results
US 7,889,535 B2Granted
F-SRAM margin screen
AssigneeTexas Instruments Incorporated
InventorsJohn A. Rodriguez, Hugh P. McAdams, Scott R. Summerfelt, Steven Bartling
Life of this patent
Estimating the term…
Abstract
A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.
Claims20
A process of testing an integrated circuit, comprising steps:
- providing a first programmable data storage component in said integrated circuit, said first programmable data storage component including:
- a first state node;
- a second state node coupled to said first state node by a state circuit, said second state node being complementary to said first state node;
- a first data ferroelectric capacitor coupled to said first state node;
- and
- a second data ferroelectric capacitor coupled to one of said first state node and said second state node;
- programming said first programmable data storage component with a first screening data value, such that said first data ferroelectric capacitor and said second data ferroelectric capacitor are polarized so as to provide data retention when power is removed from said first programmable data storage component;
- powering down said first programmable data storage component, so as to preserve polarizations in said first data ferroelectric capacitor and said second ferroelectric capacitor from said programming step;
- applying a disturb voltage to at least one of said first state node and said second state node;
- performing a recall and power up process on said first programmable data storage component;
- reading a first read data value from said first programmable data storage component;
- and
- comparing said first read data value to said first screening data value.
10 more elements
A process of testing an integrated circuit, comprising steps:
- providing a first programmable data storage component in said integrated circuit, said first programmable data storage component including:
- a first state node;
- a second state node coupled to said first state node by a state circuit, said second state node being complementary to said first state node;
- a first data ferroelectric capacitor coupled to said first state node;
- and
- a second data ferroelectric capacitor coupled to one of said first state node and said second state node;
- setting a disturb voltage at an initial value;
- programming said first programmable data storage component with a first screening data value, such that said first data ferroelectric capacitor and said second data ferroelectric capacitor are polarized so as to provide data retention when power is removed from said first programmable data storage component;
- powering down said first programmable data storage component, so as to preserve polarizations in said first data ferroelectric capacitor and said second data ferroelectric capacitor from said step of programming said first programmable data storage component;
- applying said disturb voltage to at least one of said first state node and said second state node;
- performing a recall and power up process on said first programmable data storage component;
- reading a first read data value from said first programmable data storage component;
- comparing said first read data value to said first screening data value;
- determining if said first screening data value and said first read data value meet a criterion for determining a limiting disturb voltage value;
- adjusting a value of said disturb voltage;
- and
- repeating said steps of:
- programming said programmable data storage component with said first screening data value;
- powering down said programmable data storage component;
- applying said adjusted disturb voltage to at least one of said first state node and said second state node;
- performing said recall and power up process on said first programmable data storage component;
- reading a first iterative read data value from said programmable data storage component;
- and
- comparing said first iterative read data value to said first screening data value;
- and
- determining if said first iterative read data value and said first screening data value meet said criterion for determining said limiting disturb voltage value.
23 more elements
Dependencies are inferred from the claim text.