Semiconductor integrated circuit for supporting a test mode

A semiconductor integrated circuit for supporting a test mode, comprising:

• a program region including at least one One Time Programmable Cell Array;
• and
• a program region control unit configured to activate the program region in response to an enabled fuse signal of a fuse corresponding to the program region, and to activate the program region in response to a test mode signal of the program region,
• wherein a program mode of the program region is activated to provide the activated flag signal when the program region responds to the enabled fuse signal.

A semiconductor integrated circuit for supporting a test mode, comprising:

• a plurality of program regions, each including at least one One Time Programmable Cell Array;
• a fuse unit including a plurality of fuses, each corresponding to one of the plurality of program regions;
• and
• a program region control unit configured to determine a program mode operation for one of the plurality of program regions when one of the plurality of fuses corresponding to the one of the plurality of program regions is rendered to a non-conductive state, and to determine initiation of a test mode operation in response to a test mode signal for the one of the plurality of program regions corresponding to the one of the plurality of fuses on conductive state.

A semiconductor integrated circuit for supporting a test mode, comprising:

• a plurality of banks, each including a memory cell array;
• a plurality of column decoders configured to select a plurality of bit lines for each of the plurality of banks;
• a plurality of program regions, each corresponding to one of the plurality of banks and each including at least one One Time Programmable Cell Array;
• and
• a program region control unit configured to control activation of a plurality of word lines of the plurality of program regions,
• wherein during a program mode and a test mode, the plurality of bit lines in the plurality of program regions are selected by the plurality of column decoders and the plurality of word lines are selected by the program region control unit, and
• wherein the program region control unit includes a plurality of control units, each corresponding to one of the plurality of program regions.

A semiconductor integrated circuit for supporting a test mode, comprising:

• a fuse unit;
• a plurality of banks, each including a memory cell array;
• a plurality of column decoders configured to select a plurality of bit lines for each of the plurality of banks;
• a plurality of program regions, each corresponding to one of the plurality of banks and each including at least one One Time Programmable Cell Array;
• and
• a program region control unit configured to control activation of a plurality of word lines of the plurality of program regions,
• wherein during a program mode and a test mode, the plurality of bit lines in the plurality of program regions are selected by the plurality of column decoders and the plurality of word lines are selected by the program region control unit, and
• wherein the fuse unit includes:
• a fuse box including a plurality of the fuses, each corresponding to one of the plurality of program regions;
• and
• a fuse signal generating section connected to the fuse box to provide a plurality of fuse signals, each corresponding to one of the plurality of program regions, when the fuse is rendered to the non-conductive state.