Hardware architecture for video conferencing

A video processing system that transmits a scaled video image to different scaling levels for a multipoint control unit, comprising:

• a plurality of processors configured to perform processing of video data;
• a plurality of links interconnecting the plurality of processors;
• a plurality of stream processors configured to perform video scaling of the video data as it passes between the plurality of processors over the links;
• and
• a memory that stores a network map holding data representative of a network topology, wherein the plurality of stream processors make scaling decisions with reference to the map.

A method of transmitting a scaled video image to different destinations at different respective scaling levels comprising:

• receiving video data at an MCU (multipoint control unit);
• processing the video data with a plurality of processors included in the MCU, the plurality of processors being interconnected by a plurality of links;
• processing, with a plurality of stream processors included in the MCU, data as it passes between the plurality of processors over the plurality of links;
• storing a network map holding data representative of a network topology;
• performing, at the MCU, video scaling of the video data in a first of the stream processors to a first scale level required by a first destination and performing subsequent scaling of the video data using a second stream processor to a second, smaller scaling level for a second destination;
• and
• making scaling decisions with reference to the map.

A non-transitory computer readable medium encoded with computer program instructions for routing video data, which when executed by a multipoint control unit (MCU) causes the MCU to execute a method comprising:

• receiving video data at the MCU;
• processing the video data with a plurality of processors included in the MCU, the plurality of processors being interconnected by a plurality of links;
• processing, with a plurality of stream processors included in the MCU, data as it passes between the plurality of processors over the plurality of links;
• storing a network map holding data representative of a network topology;
• performing video scaling of the video data in a first stream processor to a first scale level required by a first destination and performing subsequent scaling of the video data using a second stream processor to a second, smaller scaling level for a second destination;
• and
• making scaling decisions with reference to the map.