Differential amplifier circuit having offset adjustment circuit

A differential amplifier circuit, comprising:

• a transistor pair which constitutes a differential pair;
• a first offset adjustment circuit including a plurality of first transistors being substantially identical including with respect to a substantially same size, in order to adjust an offset produced by the transistor pair;
• and
• a second offset adjustment circuit including a plurality of second transistors which have a transistor size greater than the size of the first transistors, in order to adjust the offset produced by the transistor pair.

An offset adjusting circuit for a differential amplifier circuit including an offset adjusting circuit to adjust an offset generated by a differential pair, the offset adjusting circuit comprising:

• a fine adjustment cell section on each side of the differential pair, each of the fine adjustment cell sections including a plurality of first transistors having substantially a same transistor size and substantially a same adjustment resolution;
• and
• a shift cell section on each side of the differential pair, each of the shift cell sections including a plurality of second transistors, each of the plurality of second transistors having a size greater than a size of each one of the plurality of first transistors of the fine adjustment cell section,
• wherein each transistor of the plurality of first transistors is a fixed resolution transistor and each transistor of the plurality of second transistors is a weighted transistor, and
• wherein the first transistors have less variation of adjustment resolution than the second transistors.