Clock distribution network

An apparatus comprising:

• a bias generator configured to generate a bias voltage based on a function of a resistor and an adjustable current, the adjustable current generated based on a band gap reference generator;
• and
• a clock path including a current-mode logic divider circuit configured to generate differential clock signals, the current-mode logic divider circuit including at least one transistor having a gate responsive to the bias voltage, wherein the clock path further includes:
• a converter configured to convert the differential clock signals into single-ended clock signals;
• and
• complementary-metal-oxide semiconductor (CMOS) inverters to provide the single-ended clock signals to multiple clock trees of the clock path.

An apparatus comprising:

• a bias generator configured to generate a bias voltage based on a function of a resistor and an adjustable current, the adjustable current generated based on a band gap reference generator;
• and
• a clock path including a current-mode logic divider circuit configured to generate differential clock signals, the current-mode logic divider circuit including at least one transistor having a gate responsive to the bias voltage, wherein the clock path further includes:
• current-mode logic buffers to provide the differential clock signals to multiple clock trees of the clock path;
• and
• a converter configured to convert the differential clock signals into single-ended clock signals after the differential clock signals are provided by the current-mode logic buffers.

An apparatus comprising:

• a bias generator configured to generate a bias voltage based on a function of a resistor and an adjustable current, the adjustable current generated based on a band gap reference generator;
• and
• a clock path including a current-mode logic divider circuit configured to generate differential clock signals, the current-mode logic divider circuit including at least one transistor having a gate responsive to the bias voltage, wherein the clock path includes:
• a first receiver to receive a first differential clock signal that is used to generate the differential clock signals;
• at least one current-mode logic buffer to provide the first differential clock signal to capture data;
• and
• complementary-metal-oxide semiconductor (CMOS) inverters to generate clock signals to deserialize data.

A method comprising:

• receiving a first differential clock signal;
• generating second differential clock signals based on the first differential clock signal;
• generating a bias voltage based on a relationship between a first voltage generated based on a band gap reference generator and a second voltage generated based on the band gap reference generator;
• and
• using the bias voltage to control a gate of a transistor of at least one current-mode logic component that generates the second differential clock signals.