Phase locked loop charge pump reference current bootstrapping

#The present invention relates to phase locked loops. More particularly, the present invention relates to generating reference currents in phase locked loop charge pumps.

#A phase locked loop (PLL) is a negative feedback circuit that synchronizes the edges of a local clock with the edges of a reference clock. A PLL aligns the phases and frequencies of the clocks and helps to eliminate skew and jitter. A typical supply-regulated PLL includes a charge pump that translates control signals into an output voltage that controls a voltage-controlled oscillator (VCO) which outputs the local clock. The “up” and “down” control signals input into the charge pump denote when the local clock lags or leads the reference clock, respectively. If an “up” signal is received, the charge pump outputs a higher voltage that causes the VCO to output an increased frequency, and conversely, if a “down” signal is received, the charge pump outputs a lower voltage that causes the VCO to output a decreased frequency.

#The charge pump relies on the generation of an internal reference current to create the output voltage that is sent to the VCO. Two current sources, a source current and a sink current, may be referenced and mirrored to the reference current, which is preferably constant over all operating conditions and manufacturing process corners, in order to improve the stability and open-loop phase margin of the PLL. The two current sources may source or sink current to vary the output voltage, based on the “up” and “down” signals. Reducing variability in the reference current directly translates into improved stability and phase margin of the PLL. Existing reference current generators may be strongly influenced by variations in the supply voltage, temperature, and/or process corner, leading to decreased stability and phase margin of the PLL. The reference current could also be generated using a circuit based on a bandgap voltage reference, but such circuits may consume significant power and require a large die area.

#FIG. 1 is a block diagram of a phase-locked loop circuit with a charge pump of an embodiment.

#FIG. 2 is a schematic of a charge pump of an embodiment.

#FIG. 3 is a block diagram of a charge pump of an embodiment.

#The disclosure can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the teachings of the invention. Moreover, in the figures, like-referenced numerals designate corresponding parts or elements throughout the different views.

#By way of overview, the embodiments described herein relate to circuits and methods for generating a reference current in a charge pump. The charge pump is preferably used in a PLL, but may be used in other circuits to create a higher or lower voltage power source. In the circuits and methods disclosed in these embodiments, a reference current is generated in the charge pump based on the feedback of a charge voltage that is output from the charge pump. The reference current may be comprised of an auxiliary current and a bootstrap current. An auxiliary resistor always generates the auxiliary current because it is directly coupled to the supply voltage. A current mirror may mirror the auxiliary current so that a source current and a sink current are substantially the same as the auxiliary current. The source current or sink current may then produce a charge voltage. The charge voltage may be coupled to a gate of a transistor configured as a source follower, which may also be coupled to a bootstrap resistor. The resistance value of the bootstrap resistor may be relatively low compared to the resistance value of the auxiliary resistor. The bootstrap resistor generates a bootstrap current based on the charge voltage and supply voltage. The bootstrap current becomes a primary component of the reference current, and the source and sink currents become substantially the same as the reference current because of the current mirror. These circuits and methods may reduce the influence that variations in supply voltage, temperature, and process corner may have on the charge pump and the PLL. In addition, these circuits and methods may provide improved stability and phase margin for the PLL using little additional area at a low power.

#FIG. 1 is a block diagram of a phase-locked loop (PLL) circuit 100. The PLL 100 may include a reference clock input CKI 102, a phase frequency detector (PFD) 104, a charge pump 106, a loop filter 108, a voltage regulator 110, a voltage-controlled oscillator (VCO) 112, a clock output CKO 114, and a divider block 116. The PFD 104 may compare the phase of the reference clock CKI 102 with the phase of a divided output clock 118. The PFD 104 may output UP or DOWN corrective control signals to the charge pump 106 which may vary the charge voltage VCHG output from the charge pump 106. The UP and DOWN control signals may comprise a pulse width modulated signal or may be another type of signal that may be provided to the charge pump 106 to vary the charge voltage VCHG. The PFD 104 outputs an UP signal when the divided output clock 118 lags the reference clock CKI 102, and outputs a DOWN signal when the divided output clock 118 leads the reference clock CKI 102. In turn, the charge pump 106 may use the UP or DOWN signals to adjust a charge voltage VCHG. The charge voltage VCHG, after filtering and regulating, may control the VCO 112 to increase or decrease the frequency of the output clock CKO 114 so that it matches the reference clock CKI 102, and so that the phase difference between the two clocks is substantially zero. If an UP signal is received by the charge pump 106, the charge voltage VCHG may increase. If a DOWN signal is received by the charge pump 106, the charge voltage VCHG may decrease.