Predetermined duty cycle signal generator

A method for generating an output signal having a predetermined duty cycle, the method comprising:

• counting a first number of cycles of a signal derived from an oscillator signal;
• generating a transition in a first output signal after the first number of cycles is counted;
• counting a second number of cycles of the oscillator signal, the second number being greater than the first number;
• generating a transition in a second output signal after the second number of cycles is counted;
• resetting the counting of the first and second numbers upon a transition in the second output signal;
• generating a transition in the output signal from a first state to a second state upon a transition in the first output signal;
• and
• generating a transition in the output signal from the second state to the first state upon a transition in the second output signal.

An apparatus for generating an output signal having a predetermined duty cycle, the apparatus comprising:

• means for counting a first number of cycles of a signal derived from an oscillator signal, and for generating a transition in a first output signal after the first number of cycles is counted;
• means for counting a second number of cycles of the oscillator signal greater than the first number, and for generating a transition in a second output signal after the second number of cycles is counted;
• means for resetting the counting the first and second numbers upon a transition in the second output signal;
• and
• means for generating a transition in the output signal from a first state to a second state upon a transition in the first output signal, and for generating a transition in the output signal from the second state to the first state upon a transition in the second output signal.

A computer program product storing code for causing a computer to generate an output signal having a predetermined duty cycle, the code comprising:

• code for causing a computer to count a first number of cycles of a signal derived from an oscillator signal and generate a transition in a first output signal after the first number of cycles is counted;
• code for causing a computer to count a second number of cycles of the oscillator signal greater than the first number and generate a transition in a second output signal after the second number of cycles is counted;
• code for causing a computer to reset the count of the first and second numbers upon a transition in the second output signal;
• and
• code for causing a computer to generate a transition in the output signal from a first state to a second state upon a transition in the first output signal and generate a transition in the output signal from the second state to the first state upon a transition in the second output signal.

A device for wireless communications, the device comprising at least one digital-to-analog converter (DAC) for converting a digital TX signal to an analog TX signal, at least one baseband TX amplifier for amplifying the analog TX signal, a TX LO signal generator, an upconverter coupled to the TX LO signal generator and the at least one baseband TX amplifier, a TX filter coupled to the output of the upconverter, a power amplifier (PA) coupled to the TX filter, an RX filter, a low-noise amplifier (LNA) coupled to the RX filter, an RX LO signal generator, a downconverter coupled to the RX LO signal generator and the RX filter, at least one low-pass filter coupled to the output of the downconverter, at least one analog-to-digital converter (ADC) for converting the output of the low-pass filter into a digital signal, a clock signal generator, at least one of the DAC and the ADC being driven by a clock signal generated by the clock signal generator, the clock signal generator comprising:

• a first counter configured to count a first number of cycles of a signal derived from an oscillator signal, the output signal of the first counter configured to transition after the first number of cycles is counted;
• a second counter configured to count a second number of cycles of the oscillator signal, the output signal of the second counter configured to transition after the second number of cycles is counted, the first and second counters configured to be reset upon a transition in the output signal of the second counter;
• and
• a toggle latch configured to generate the clock signal, the output signal of the toggle latch configured to transition from a first state to a second state upon a transition in the output signal of the first counter, the output signal of the toggle latch further configured to transition from the second state to the first state upon a transition in the output signal of the second latch.