US 7,888,982 B2 · Semiconductor memory apparatus

Abstract

A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals.

Claims16

Dependent claims

A semiconductor apparatus, comprising:

a delay locked loop (DLL) circuit configured to delay a clock signal to generate a DLL clock signal;
a phase locked loop (PLL) circuit configured to receive the DLL clock signal to generate a PLL clock signal, wherein the activation of the PLL circuit is determined based on the DLL clock signal;
and
a data output buffer configured to buffer output data signals according to one of the DLL clock signal and the PLL clock signal.

1 more element

A semiconductor apparatus, comprising:

a delay locked loop (DLL) circuit configured to negatively delay a clock signal to generate a DLL clock signal;
a phase locked loop (PLL) circuit configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal having a frequency corresponding to a level of the control voltage;
a frequency discrimination unit configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal;
and
a data output buffer configured to buffer output data signals according to one of the DLL clock signal and the PLL clock signal.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/855,244Filed 12 Aug 2010 · continuation

Priority

KR 10-2008-011089210 Nov 2008

Published

US 2010/0117695 A12 Dec 2010

Granted

15 Feb 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
H03L 7/0995
Concerning mainly the controlled oscillator of the loop: the oscillator comprising a ring oscillator
H03L 7/0812
Provided with an additional controlled phase shifter: and where no voltage or current controlled oscillator is used
H03L 2207/06
Indexing scheme relating to automatic control of frequency or phase and to synchronisation: phase locked loops with a controlled oscillator having…

Family

Application12/344,799Parent of this continuation · filed 29 Dec 2008

US 2010/0301911 A1Pre-grant publication · published 2 Dec 2010

US 7,800,422 B2Parent of this continuation

US 2010/0117695 A1Published application

US 7,888,982 B2This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor memory apparatus

Life of this patent

Semiconductor memory apparatus

Life of this patent

Abstract

Claims16