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US 7,888,973 B1Granted
Matrix time-to-digital conversion frequency synthesizer
AssigneeMarvell International Ltd.
InventorsFrancesco Rezzi, Antonio Liscidini
Life of this patent
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Abstract
The present disclosure provides for a time to digital converter (TDC). The time to digital converter can include a reference ingress that receives a reference signal and passes the reference signal through multiple delay elements, a clock signal ingress that receives a clock signal and passes the clock signal through another set of delay elements, and multiple comparators, which are fewer in number than the total number of delay elements. The multiple comparators 1) receive the delayed reference and delayed clock signals and 2) output a set of comparison results for comparisons of pairs of delayed references and delayed clock signals.
Claims37
A time to digital converter, comprising:
- a reference ingress that receives a reference signal and passes the reference signal through a plurality of first delay elements;
- a clock signal ingress that receives a clock signal and passes the clock signal through a plurality of second delay elements;
- and
- a plurality of comparators, coupled to the first and second delay elements, that are configured to receive a plurality of delayed reference and delayed clock signals, each comparator further configured to output a comparison result that indicates the comparison between a pair of delayed reference and delayed clock signals, wherein a total number of the first delay elements plus the second delay elements is less than a number of the plurality of comparators.
1 more element
A method of digitizing a time difference, comprising:
- delaying a reference signal in a plurality of first delay elements;
- delaying a clock signal in a plurality of second delay elements;
- and
- comparing pairs of delayed reference and delayed clock signals in a plurality of comparators that exceeds a total number of the first delay elements plus the second delay elements.
1 more element
A time to digital converter, comprising:
- a first delay line that includes a plurality of first delay elements, the first delay line receiving a reference signal and delays the reference signal by a plurality of first delays;
- a second delay line that includes a plurality of second delay elements, the second delay line receiving a clock signal having a clock period and delays the clock signal by a plurality of second delays that are different than the first delays;
- and
- a matrix memory, coupled to the first and second delay lines, that stores a plurality of delayed reference signals at each of a plurality of sampling instants of the delayed clock signals.
1 more element
A frequency synthesizer, comprising:
- a time to digital converter that includes:
- a first delay line that includes a plurality of first delay elements, the first delay line receiving a reference signal and delays the reference signal by a plurality of first delays;
- a second delay line that includes a plurality of second delay elements, the second delay line that receives a divided clock signal having a divided clock period, the second delay line delaying the divided clock signal by a plurality of second delays different than the first delays, a total delay of the first delay line and a total delay of the second delay line equaling the divided clock period;
- and
- a matrix memory, coupled to the first and second delay lines, that samples a plurality of delayed reference signals at each of a plurality delayed divided clock signals and encodes a time delay difference between the reference signal and the divided clock signal based on the sampled delayed reference signals;
- a digital filter that is configured to shape a spectrum of the time delay difference to generate a digital control word;
- a digitally controlled oscillator that is configured to generate an oscillatory output signal having an output signal period based on the digital control word;
- a divider that is configured to generate the divided clock signal by dividing a frequency of the oscillatory output signal by a multiple;
- and
- a controller that is configured to adjust the multiple based on a predetermined ratio between the clock period and the output signal period.
7 more elements
A frequency locked loop, comprising:
- an input adder that is configured to subtract a feedback word from a frequency control word to generate a frequency error;
- a digital filter that is configured to shape a spectrum of the frequency error to generate a filtered frequency error;
- a digitally controlled oscillator that is configured to generate an oscillatory output signal having a frequency that is based on the filtered frequency error;
- a time to digital converter that is configured to digitize a time difference between the oscillatory output signal and a reference signal, the time to digital converter including:
- a first delay line that includes a plurality of first delay elements, the first delay line receiving a reference signal and delays the reference signal by a plurality of first delays;
- a second delay line that includes a plurality of second delay elements, the second delay line that receives a divided clock signal having a divided clock period, the second delay line delaying the divided clock signal by a plurality of second delays different than the first delays, a total delay of the first delay line and a total delay of the second delay line equaling the divided clock period;
- and
- a matrix memory, coupled to the first and second delay lines, that samples a plurality of delayed reference signals at each of a plurality delayed divided clock signals and encodes a time delay difference between the reference signal and the divided clock signal based on the sampled delayed reference signals;
- and
- a digital differentiator that is configured to generate the feedback word by differentiating the time difference.
7 more elements
A method of generating a clock signal, comprising:
- delaying a reference signal that has a reference signal period by a plurality of first delays;
- delaying the clock signal by a plurality of second delays, to generate a plurality of delayed clock signals, the second delays differing from the first delays such that a total delay of the reference signal and a total delay of the clock signal equals the reference signal period;
- storing a plurality of delayed reference signals at each of a plurality of sampling instants of the delayed clock signals;
- and
- encoding a digital word that digitizes a time delay difference between the reference signal and the clock signal based on the stored plurality of delayed reference signals.
2 more elements
Dependencies are inferred from the claim text.