Logic circuits, inverter devices and methods of operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHuaxiang Yin, Youngsoo Park, Jaechul Park, Sunil Kim
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Abstract
An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor.
Claims21
An inverter device comprising:
- at least a first transistor connected between a power source node and ground, the first transistor including a first gate and a first terminal that are capacitively-coupled internal to the first transistor to control a boost voltage at a boost node, the first terminal being one of a first source and a first drain of the first transistor;
- wherein
- a plurality of transistors are connected between the power source node and ground, the plurality of transistors including,
- the first transistor, wherein a power voltage is applied to the first drain,
- a second transistor including a second gate, a second source, and a second drain, wherein an input voltage is applied to the second gate, and the second drain is connected to the first source at an output node through which an output voltage is output, and
- a third transistor including a third gate, a third source, and a third drain, wherein the power voltage is applied to the third gate and the third drain, and the third source is connected to the first gate, and the first gate and the first source are internally capacitive-coupled in the first transistor to control the boost voltage at the boost node, and the third gate and the third source are internally capacitive-coupled by a first parasitic capacitance resulting from an overlap between the third gate and the third source.
A method of operating an inverter device including at least a first transistor connected between a power source node and ground, the first transistor including a first gate and a first terminal that are capacitively-coupled internal to the first transistor to control a boost voltage at a boost node, the first terminal being one of a first source and a first drain of the first transistor, wherein a plurality of transistors are connected between the power source node and ground, and wherein the plurality of transistors include,
- the first transistor, wherein a power voltage is applied to the first drain,
- a second transistor including a second gate, a second source, and a second drain, wherein an input voltage is applied to the second gate, and the second drain is connected to the first source at an output node through which an output voltage is output, and
- a third transistor including a third gate, a third source, and a third drain, wherein the power voltage is applied to the third gate and the third drain, and the third source is connected to the first gate, the method comprising:
- controlling a size of the boost voltage by a first parasitic capacitance formed by the overlap between the first gate and the first terminal, the boost voltage being induced on the first gate of the first transistor;
- wherein
- the size of the boost voltage is further controlled by a second parasitic capacitance resulting from an overlap between the third gate and the third source.
Dependencies are inferred from the claim text.