Verification support system and method
AssigneeFujitsu Limited
InventorHiroaki Iwashita
Life of this patent
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Abstract
A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock. The system includes an identification unit to identify whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of logic gates of the receiver clock domain to combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic.
Claims12
A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain including a plurality of logic gates driven by a transmitter clock and a plurality of outputs for transmitting data, the receiver clock domain including a plurality of logic gates driven by a receiver clock, a plurality of inputs coupled to the outputs of the transmitter domain for receiving transmitted data, and a combinational logic coupled to at least one of the logic gates of the receiver domain, the system comprising:
- a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock;
- and
- an identification unit for identifying whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of the logic gates of the receiver clock domain to the combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic.
A verification support method for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain including a plurality of logic gates driven by a transmitter clock and a plurality of outputs for transmitting data, the receiver clock domain including a plurality of logic gates driven by a receiver clock, a plurality of inputs coupled to the outputs of the transmitter domain for receiving transmitted data, and a combinational logic coupled to at least one of the logic gates of the receiver domain, the method comprising:
- receiving data to be transmitted from the transmitter clock domain;
- detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock;
- and
- identifying whether or not any fluctuation of the data determined by the detection is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of the logic gates of the receiver clock domain to the combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic.
A storage medium storing a verification support program allowing a processor of a computer to execute logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain including a plurality of logic gates driven by a transmitter clock and a plurality of outputs for transmitting data, the receiver clock domain including a plurality of logic gates driven by a receiver clock, a plurality of inputs coupled to the outputs of the transmitter domain for receiving transmitted data, and a combinational logic coupled to at least one of the logic gates of the receiver domain, the program allowing the processor to execute an operation, the operation comprising:
- receiving data to be transmitted from the transmitter clock domain;
- detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock;
- and
- identifying whether or not any fluctuation of the data detected by the detection is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of the logic gates of the receiver clock domain to the combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic.
Dependencies are inferred from the claim text.