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US 7,888,806 B2Granted
Electrical connections for multichip modules
AssigneeSamsung Electronics Co., Ltd.
InventorsSeok-Chan Lee, Min-Woo Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a first semiconductor chip mounted on a substrate and a second semiconductor chip mounted on top of the first semiconductor chip. The first chip includes a plurality of metal lines which may be deposited at its top surface, and the metal lines are isolated from circuitry in the first chip. Wire bonds connect pads on the second chip to metal lines on the first chip. Additional wired bonds connect the metal lines on the first chip to terminals on the substrate. Conductive through-silicon vias or solder bumps may replace the wire bonds, and additional chips may be included in the package.
Claims24
A semiconductor package comprising:
- a package substrate having first terminals and second terminals;
- a semiconductor chip mounted on the package substrate, the semiconductor chip comprising:
- a semiconductor substrate;
- internal circuitry formed on the semiconductor substrate;
- a dielectric layer formed on the internal circuitry;
- a plurality of chip pads disposed on the dielectric layer and in electrical communication with the internal circuitry;
- a passivation layer formed on the dielectric layer and the chip pads, the passivation layer having an opening to expose a portion of one of the chip pads;
- and
- a conductive line disposed on the dielectric layer, the conductive line being substantially electrically isolated from the internal circuitry and any other circuits internal to the semiconductor chip;
- a first electrical connection formed between the conductive line and one of the first terminals;
- and
- a second electrical connection connecting one of the chip pads to one of the second terminals through the opening.
9 more elements
A semiconductor package comprising:
- a package substrate having first terminals and second terminals;
- a first memory chip mounted on the package substrate, the first memory chip comprising:
- a semiconductor substrate;
- internal circuitry formed on the semiconductor substrate;
- a dielectric layer formed on the internal circuitry;
- a plurality of first chip pads consisting of all chip pads of the first memory chip, at least a portion of the first chip pads being disposed on the dielectric layer and in electrical communication with the internal circuitry;
- a passivation layer formed on the dielectric layer and the at least a portion of the first chip pads, the passivation layer having a first opening to expose a portion of one of the first chip pads;
- and
- a conductive line disposed on the dielectric layer, the conductive line being substantially electrically isolated from the first chip pads;
- a first electrical connection formed between the conductive line and one of the first terminals;
- and
- a second electrical connection connecting one of the first chip pads to corresponding one of the second terminals through the first opening.
9 more elements
A semiconductor package comprising:
- a package substrate having first terminals and second terminals;
- a first semiconductor chip mounted on the package substrate, the first semiconductor chip comprising:
- a semiconductor substrate;
- internal circuitry formed on the semiconductor substrate;
- a dielectric layer formed on the internal circuitry;
- a plurality of first chip pads disposed on the dielectric layer and in electrical communication with the internal circuitry;
- a passivation layer formed on the dielectric layer and the first chip pads, the passivation layer having a first opening to expose a portion of one of the first chip pads;
- and
- a conductive line disposed on the dielectric layer, the conductive line being disconnected from the first chip pads and any other chip pads of the first semiconductor chip;
- a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip having a plurality of second chip pads;
- a first electrical connection formed between the conductive line and one of the first terminals;
- a second electrical connection connecting one of the first chip pads to corresponding one of the second terminals through the first opening;
- and
- a third electrical connection electrically connecting one of the second chip pads to the conductive line.
11 more elements
Dependencies are inferred from the claim text.