US 7,888,802 B2 · Bonding pad structure and manufacturing method thereof

Abstract

A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of lower wiring layers disposed in the interlayer insulation layer between the upper wiring layer and the substrate and configured to prevent the interlayer insulation layer from cracking especially during a wire bonding process in which a wire is bonded to the upper wiring layer. For example, the respective areas occupied by the lower wiring layers sequentially increase in the interlayer insulation layer in a downward direction from the upper wiring layer towards the substrate. Also, each of the lower wiring layers may project further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer.

Claims18

Dependent claims

A bonding pad of a semiconductor device, comprising:

a substrate;
an interlayer insulation layer disposed on the substrate;
an upper layer of wiring disposed on the interlayer insulation layer;
and
a plurality of lower layers of wiring juxtaposed one above the other in the interlayer insulation layer between the upper layer of wiring and the substrate, the lower layers of wiring being electrically conductively connected to the upper layer of wiring at a bottom surface of the upper layer of wiring that faces toward the substrate, and
wherein the respective areas occupied by the lower layers of wiring sequentially increase in the interlayer insulation layer in a downward direction from the upper layer of wiring towards the substrate, and each of the lower layers of wiring projects further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer.

3 more elements

A bonding pad of a semiconductor device, comprising:

a substrate;
a first interlayer insulation layer disposed on the substrate;
a first lower layer of wiring having a first opening therethrough and disposed on the first interlayer insulation layer;
a second interlayer insulation layer disposed on the first lower layer of wiring and buried in the first opening;
a second lower layer of wiring having a second opening therethrough and disposed on the second interlayer insulation layer, the second opening being wider than the first opening;
a third interlayer insulation layer disposed on the second lower layer of wiring and buried in the second opening;
and
an upper layer of wiring disposed on the third interlayer insulation layer and spanning a region of the bonding pad over the second opening.

5 more elements

Dependencies are inferred from the claim text.

Bonding pad structure and manufacturing method thereof

Life of this patent

Bonding pad structure and manufacturing method thereof

Life of this patent

Abstract

Claims18