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US 7,888,796 B2Granted
Controller chip mounted on a memory chip with re-wiring lines
AssigneeRenesas Electronics Corporation
InventorMinoru Shinohara
Life of this patent
Estimating the term…
Abstract
A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.
Claims17
A semiconductor device comprising:
- a plurality of memory chips stacked and each having a plurality of pads formed along two opposed sides of a main surface thereof;
- a microcomputer chip mounted over the memory chip located at the top stage out of the memory chips;
- and
- a plurality of external terminals coupled electrically to the microcomputer chip,
- wherein each of the memory chips includes:
- first pads formed over the main surface thereof along one of the two opposed sides of the main surface;
- lead-out wiring lines coupled electrically to the first pads;
- second pads formed over the main surface of the memory chip along the other of the two opposed sides of the main surface and coupled electrically to the lead-out wiring lines;
- and third pads coupled electrically to terminals of the microcomputer chip through wires over the lead-out wiring lines, and
- wherein, among the stacked memory chips, the second pads of the memory chip located at an upper stage and the second pads of the memory chip located at a lower stage and projected and exposed from the upper-stage memory chip are coupled together electrically using wires.
7 more elements
A semiconductor device comprising:
- a substrate, the substrate having a chip mounting portion and a plurality of terminals formed around the chip mounting portion;
- a memory chip mounted over the chip mounting portion of the substrate, the memory chip having a quadrangular plane shape and having a main surface with a plurality of pads formed thereon;
- a microcomputer chip mounted over the main surface of the memory chip, the microcomputer chip having a quadrangular plane shape and having a main surface with a plurality of electrodes formed thereon;
- a plurality of first wires for coupling the electrodes of the microcomputer chip and the pads of the memory chip electrically with each other;
- and
- a plurality of second wires for coupling the pads of the memory chip and the terminals of the substrate electrically with each other,
- wherein the microcomputer chip is mounted over the memory chip in such a manner that one side thereof stand side by side with one side of the memory chip,
- wherein the pads of the memory chip include a plurality of first pads formed along the one side of the memory chip, a plurality of second pads positioned closer to the microcomputer chip than the first pads, and a plurality of wiring lines for coupling between the first pads and the second pads wherein the pads of the memory chip include a plurality of third pads formed along a side intersecting the one side of the memory chip, a plurality of fourth pads positioned closer to the microcomputer chip than the third pads, and a plurality of wiring lines for coupling the third pads and the fourth pads with each other, wherein the electrodes of the microcomputer chip include a plurality of electrodes for external interface formed along a side intersecting the one side of the microcomputer chip to perform input and output of data for the exterior of the system, wherein the first wires include a plurality of wires for external interface to couple the microcomputer chip and the exterior of the system electrically with each other, wherein the electrodes for external interface of the microcomputer chip and the fourth pads are coupled together electrically through the wires for external interface, and wherein the third pads of the memory chip and the terminals of the substrate are coupled together electrically through the second wires,
- wherein the electrodes of the microcomputer chip include a plurality of electrodes for internal interface to perform input and output of data for the interior of the system comprised of the memory chip and the microcomputer chip,
- wherein the first wires include a plurality of wires for internal interface to couple the microcomputer chip and the memory chip electrically with each other, and
- wherein the electrodes for internal interface of the microcomputer chip and the second pads are coupled electrically with each other through the wires for internal interface.
8 more elements
Dependencies are inferred from the claim text.