Semiconductor device and method

A semiconductor device, comprising:

• a semiconductor substrate;
• an active region in the semiconductor substrate and comprising a first terminal region and a second terminal region;
• an inactive region interrupting the active region and configured such that an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region;
• a metallization layer on a surface of the semiconductor device and at least partly overlapping the active area, the metallization layer including a first part and second part separated by a gap;
• wherein the first part is in electrical contact to the first terminal region, and the second part is in electrical contact to the second terminal region;
• and
• means for reducing an electrical power dissipation below the gap compared to an electrical power dissipation below the first part and the second part of the metallization layer.

A DMOS device comprising:

• an active region in a semiconductor substrate of a first conductivity type with a body zone of a second conductivity type, comprising a source terminal region of the first conductivity type and a controllable channel region formed in the body zone and a drain terminal region of the first conductivity type in the semiconductor substrate, wherein the active region is interrupted by an inactive region with a reduced or non-electrical power dissipation compared to a power dissipation in the active region;
• and
• a metallization layer for heat dissipation caused by the active region and for the power supply of the active region, arranged above the active region on the upper surface of the DMOS device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the source terminal region, and a second part, in electrical contact to the drain terminal region, wherein the first and the second part are separated by a gap;
• and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to a power dissipation below the first part and the second part of the metallization layer.

A method of manufacturing a semiconductor device, comprising:

• producing an active region in a semiconductor substrate comprising a first terminal region and a second terminal region, the active region being interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than a power dissipation in the active region;
• and
• applying a metallization layer arranged with respect to an active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap;
• and wherein the applying is performed so that the gap and the inactive region is mutually arranged so that therewith an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first and the second part of the metallization layer.