US 7,888,791 B2Granted

Device for electrical connection of an integrated circuit chip

AssigneeSTMicroelectronics S.r.l.

InventorsPierre Bormann, Luc Morineau, Jacques Chavade

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Abstract

A device is provided for electrically connecting an integrated circuit chip. The device includes a main board, an intermediate board, and electrical connection balls in a space separating the boards. In the space, a peripheral zone comprises a peripheral matrix of balls, a central zone comprises a central matrix of balls, a first secondary zone comprises a matrix of electrical connection vias linked to the balls of the two adjacent rows of balls of the peripheral matrix, and a second secondary zone comprises a matrix of electrical connection vias linked to balls of the central matrix. The first secondary zone and the second secondary zone are separated by an intermediate zone that includes at least a first part having at least one complementary row of electrical connection balls, and a second part having complementary electrical connection vias linked to the balls of this complementary row.

Claims16

Dependent claims

An information processing system including at least one integrated circuit chip and at least one electrical connection device, the electrical connection device comprising:

a main board including electrical connection pads and electrical connection tracks on a first face, the main board also including electrical connection vias;
an intermediate board including first electrical connection pads on a first face for connection of the chip, second electrical connection pads on a second face, and electrical connections between the first and second pads;
and
electrical connection balls located in a space separating the main board and the intermediate board, the electrical connection balls being interposed between the pads of the main board and the second pads of the intermediate board,
wherein a peripheral zone of the space comprises a peripheral matrix of four rows of balls on a peripheral side of the space, the rows of the matrix being defined in a longitudinal direction,
a central zone of the space comprises a central matrix of balls,
a first secondary zone of the space is adjacent to the peripheral zone of the space, the first secondary zone comprising a matrix of two rows of electrical connection vias made in the main board and linked by the electrical connection tracks to respective balls of the two adjacent rows of balls of the peripheral matrix,
a second secondary zone of the space comprises a matrix of at least two rows of electrical connection vias made in the main board and linked by the electrical connection tracks to respective balls of the central matrix,
the first secondary zone and the second secondary zone are separated by an intermediate zone of the space, and
the intermediate zone is divided into at least two parts, one part of the intermediate zone comprising at least one row of electrical connection balls, and another part of the intermediate zone comprising electrical connection vias made in the main board and linked by the electrical connection tracks to respective balls of the one part of the intermediate zone.

7 more elements

An information processing system including at least one integrated circuit chip and at least one device for electrical connection, the device comprising:

a main board including pads, and vias electrically connected to the pads;
an intermediate board including first pads on a first face for connection of the chip, and second pads on a second face that are electrically connected to the first pads;
and
balls located in a space between the main board and the intermediate board, the balls being interposed between the pads of the main board and the second pads of the intermediate board,
wherein the balls comprise a peripheral matrix of at least two rows of balls on a peripheral side in a peripheral zone of the space, and a central matrix of balls in a central zone of the space, the rows of the matrix being defined in a longitudinal direction,
the vias of the main board comprise:
a first matrix of two rows of vias in a first secondary zone of the space that is adjacent to the peripheral zone of the space, the vias of the first matrix being electrically connected to respective balls of the peripheral matrix;
and
a second matrix of vias in a second secondary zone of the space, the vias of the second matrix being electrically connected to respective balls of the central matrix,
the first secondary zone and the second secondary zone are separated by an intermediate zone of the space, the intermediate zone being divided into at least first and second parts,
the balls further comprise at least one row of balls in the first part of the intermediate zone, and
the vias of the main board further comprise vias in the second part of the intermediate zone that are electrically connected to respective balls in the first part of the intermediate zone.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/543,873Filed 19 Aug 2009 · division
Priority: FR 04 1348217 Dec 2004
Published: US 2009/0310319 A117 Dec 2009
Granted: 15 Feb 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10W 70/65
Characterised by their interconnections: shapes or dispositions of interconnections
H05K 1/114
Directly combined with via connections: pad being close to via, but not surrounding the via
H10W 90/401
Package configurations: characterised by multiple insulating or insulated package substrates, interposers or RDLs
H05K 2201/09227
Conductive traces: layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting

Family

Application11/305,886Parent of this division · filed 16 Dec 2005
US 2009/0310319 A1Pre-grant publication · published 17 Dec 2009
US 7,589,411 B2Parent of this division
US 2006/0138636 A1Published application
US 7,888,791 B2This patent

From the US filing history. Foreign family members aren’t listed.