US 7,888,786 B2Granted

Electronic module comprising memory and integrated circuit processor chips formed on a microchannel cooling device

AssigneeInternational Business Machines Corporation

InventorsPaul S. Andry, Evan G. Colgan, Lawrence S. Mok, Chirag S. Patel, David E. Seeger

Life of this patent

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Abstract

Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Claims19

Dependent claims

An electronic module, comprising:

a microchannel cooling device comprising:
a plurality of coolant inlets and outlets,
a planar silicon substrate and a second silicon substrate, the planar silicon substrate includes a recessed region comprising a plurality of parallel, microscopic heat conducting fins which define a plurality of channels, and
wherein a bottom surface of the second silicon substrate is bonded to a top surface of the planar silicon substrate and the top of the fins, thereby defining a chamber for a flow of coolant through the channels between the plurality of inlet and outlets;
a first IC (integrated circuit) processor chip having a non-active surface bonded to a first surface of the microchannel cooling device;
a second IC processor chip having a non-active surface bonded to a second surface of the microchannel cooling device opposite the first surface of the microchannel cooling device,
wherein the first IC processor chip and the second IC processor chip directly communicate with one another via a communication link provided by a flexible cable connected to both the first and the second IC processor chips;
a first array of IC memory chips mounted to an active surface of the first IC processor chip;
a second array of IC memory chips mounted to an active surface of the second IC processor chip;
a first communication and input/output (CIO) module connected to the first IC processor chip via a first array of vertical pins or solder columns mounted therebetween;
and
a second communication and input/output (CIO) module connected to the second IC processor chip via a second array of vertical pins or solder columns mounted therebetween.

9 more elements

An electronic module, comprising:

a microchannel cooling device comprising at least one coolant inlet and at least one coolant outlet;
a first IC (integrated circuit) processor chip having a non-active surface bonded to a first surface of the microchannel cooling device;
a second IC processor chip having a non-active surface bonded to a second surface of the microchannel cooling device opposite the first surface of the microchannel cooling device,
wherein the first IC processor chip and the second IC processor chip directly communicate with one another via a communication link provided by a flexible cable connected to both the first and the second IC processor chips;
a first array of IC memory chips mounted to an active surface of the first IC processor chip;
a second array of IC memory chips mounted to an active surface of the second IC processor chip;
a first communication and input/output (CIO) module connected to the first IC processor chip, and wherein the first CIO module is bonded directly to a non- active surface of the first array of IC memory chips;
and
a second communication and input/output (CIO) module connected to the second IC processor chip, and wherein the second CIO module is bonded directly to a non-active surface of the second array of IC memory chips, wherein the first CIO module is connected to the first IC processor chip via a first array of vertical pins or solder columns mounted therebetween, and
wherein the second CIO module is connected to the second IC processor chip via a second array of vertical pins or solder columns mounted therebetween.

7 more elements

An electronic module, comprising:

a microchannel cooling device comprising at least one coolant inlet and at least one coolant outlet;
a first IC (integrated circuit) processor chip having a non-active surface bonded to a first surface of the microchannel cooling device;
a second IC processor chip having a non-active surface bonded to a second surface of the microchannel cooling device opposite the first surface of the microchannel cooling device,
wherein the first IC processor chip and the second IC processor chip directly communicate with one another via a communication link provided by a flexible cable connected to both the first and the second IC processor chips;
a first array of IC memory chips mounted to an active surface of the first IC processor chip;
a second array of IC memory chips mounted to an active surface of the second IC processor chip;
a first communication and input/output (CIO) module connected to the first IC processor chip via a first array of vertical pins or solder columns mounted therebetween;
and
a second communication and input/output (CIO) module connected to the second IC processor chip via a second array of vertical pins or solder columns mounted therebetween.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/735,155Filed 13 Apr 2007 · division
Priority: 12 Nov 2004
Published: US 2007/0210446 A113 Sep 2007
Granted: 15 Feb 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 40/47
Involving heat exchange by flowing fluids: by flowing liquids, e.g. forced water cooling
H10W 90/00
Package configurations
H10W 72/877
On different surfaces: bump connectors and die-attach connectors
H10W 90/288
Configurations of stacked chips: characterised by arrangements for thermal management of the stacked chips

Family

Application10/987,985Parent of this division · filed 12 Nov 2004
US 2007/0210446 A1Pre-grant publication · published 13 Sep 2007
US 7,230,334 B2Parent of this division
US 2006/0103011 A1Published application
US 7,888,786 B2This patent

From the US filing history. Foreign family members aren’t listed.