Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers

A die package structure, comprising:

• a chip-placed frame, including a plurality of chip-placed areas and a plurality of leads, wherein said plurality of leads is used to connect each said plurality of chip-placed areas and there is a gap existing between each said plurality of chip-placed areas, and each said plurality of chip-placed areas includes an adhesive layer on a top surface thereof;
• a chip including an active surface and a reverse surface, wherein said active surface includes a plurality of pads and said reverse surface is formed on said adhesive layer of each said chip-placed areas;
• a package structure surrounding said chip-placed frame and said plurality of chip, wherein said plurality of pads on said active surface are exposed;
• a plurality of patterned metal traces, wherein one end of said patterned metal trace is electrically connected to said plurality of pads and the other end of said patterned metal trace is extended and covered a surface of said package structure;
• a plurality of patterned protective layers used to cover said plurality of patterned metal traces and expose a portion of a fan-out structure of said plurality of patterned metal traces which is extended away from said active surface;
• a plurality of patterned UBM layers formed on said fan-out structure and electrically connected to said patterned metal traces;
• and
• a plurality of conductive elements formed on said plurality of patterned UBM layers and electrically connected to said plurality of patterned metal traces.