Apparatus and method configured to lower thermal stresses
AssigneeInfineon Technologies AG
InventorsPeter Nelle, Matthias Stecher
Life of this patent
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Abstract
An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.
Claims21
An apparatus comprising:
- a semiconductor chip;
- a lead frame;
- and
- a layer structure comprising at least a diffusion solder layer and a buffer layer, wherein the layer structure is arranged between the semiconductor chip and the lead frame, and
- wherein the buffer layer comprises a ductile material, which is soft in comparison to a material of the diffusion solder layer, and the buffer layer comprises a layer thickness that is greater than 500 nm and such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.
Dependencies are inferred from the claim text.