Capacitor-based method for determining and characterizing scribe seal integrity and integrity loss

An integrated circuit chip die with a scribe seal integrity detector, comprising:

• a scribe seal that extends along at least a portion of a periphery of the integrated chip die, wherein the scribe seal comprises an inner wall, and wherein the inner wall further comprises vertically extending alternating levels of metal and via electrically contacting one another;
• a detector test structure located laterally adjacent to an inner edge of the inner wall of the scribe seal facing a center portion of the integrated chip die, wherein the detector test structure and the inner wall of the scribe seal are separated by one or more dielectric materials;
• a first electrical connection between the scribe seal and at least one bond pad;
• and
• a second electrical connection between the detector test structure and at least one bond pad located in an active circuitry region;
• wherein the detector test structure is segmented into one or more independent monitoring layers respectively located within a metal layer and electrically connected to separate bond pads, each of the one or more independent monitoring layers configured to independently monitor the scribe seal integrity of the scribe seal for only the associated metal layer;
• and
• wherein the inner wall of the scribe seal and the detector test structure are configured proximately to allow one or more electrical parameters associated therewith, and wherein the first and second electrical connections are configured to be accessed for a monitoring of the one or more electrical parameters, wherein the one or more electrical parameters provides an indication related to a scribe seal integrity of the scribe seal.

An integrated circuit chip die with a scribe seal integrity detector, comprising:

• a scribe seal that extends along at least a portion of a periphery of the integrated chip die, wherein the scribe seal comprises an inner wall, and wherein the inner wall further comprises vertically extending alternating levels of metal and via electrically contacting one another;
• a detector test structure located laterally adjacent to an inner edge of the inner wall of the scribe seal facing a center portion of the integrated chip die, wherein the detector test structure and the inner wall of the scribe seal are separated by one or more dielectric materials;
• a first electrical connection between the scribe seal and at least one bond pad;
• and
• a second electrical connection between the detector test structure and at least one bond pad located in an active circuitry region;
• wherein the first electrical connection is between the inner wall of the scribe seal and at least one bond pad located in the active circuitry region;
• wherein the detector test structure further comprises alternating levels of metal and via electrically isolated from the substrate of the integrated circuit chip die;
• and
• wherein the inner wall of the scribe seal and the detector test structure are configured proximately to allow one or more electrical parameters associated therewith, and wherein the first and second electrical connections are configured to be accessed for a monitoring of the one or more electrical parameters, wherein the one or more electrical parameters provides an indication related to a scribe seal integrity of the scribe seal.

An integrated circuit chip die including a scribe seal integrity detector, comprising:

• active circuitry;
• a scribe seal structure at least partially encompassing the active circuitry;
• the scribe seal structure comprising vertically extending alternating levels of dielectric material with metal and metal-filled vias electrically contacting one another;
• a test structure at least partially encompassing the active circuitry and spaced laterally from the scribe seal structure toward the active circuitry;
• the test structure comprising vertically extending alternating levels of dielectric material with metal and metal-filled vias electrically contacting one another;
• dielectric material separating the scribe seal structure and the test structure;
• and
• at least one bond pad respectively electrically coupled to each of the scribe seal structure and the test structure;
• wherein the test structure comprises four segments, each segment coupled to a respective different bond pad;
• and
• wherein the scribe seal structure and the test structure are configured so that electrical measurements taken across the respective at least one bond pads can be used to determine an integrity of the scribe seal of the die.

An integrated circuit chip die including a scribe seal integrity detector, comprising:

• active circuitry;
• a scribe seal structure at least partially encompassing the active circuitry;
• the scribe seal structure comprising vertically extending alternating levels of dielectric material with metal and metal-filled vias electrically contacting one another;
• a test structure at least partially encompassing the active circuitry and spaced laterally from the scribe seal structure toward the active circuitry;
• the test structure comprising vertically extending alternating levels of dielectric material with metal and metal-filled vias electrically contacting one another;
• dielectric material separating the scribe seal structure and the test structure;
• and
• at least one bond pad respectively electrically coupled to each of the scribe seal structure and the test structure;
• wherein the seal structure comprises an inner wall structure and an outer wall structure, each comprising vertically extending alternating levels of dielectric material with metal and metal-filled vias, and at least one of the inner and outer wall structures is coupled to the respective at least one bond pad;
• and
• wherein the scribe seal structure and the test structure are configured so that electrical measurements taken across the respective at least one bond pads can be used to determine an integrity of the scribe seal of the die wherein the test structure comprises segments;
• each segment is coupled to a respective different bond pad;
• and the inner wall structure is coupled to the respective at least one bond pad.