Structures of high-voltage MOS devices with improved electrical performance

A semiconductor structure comprising:

• a substrate;
• a first high-voltage well (HVW) region of a first conductivity type overlying the substrate, wherein no well region is directly underlying the first HVW region;
• a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally contacting the first HVW region;
• a third HVW region of the second conductivity type underlying the second HVW region, wherein the third HVW region substantially does not extend into the region directly underlying the first HVW region, and wherein the third HVW region has a bottom substantially lower than a bottom of the first HVW region;
• an insulation region in a portion of the first HVW region and extending from a top surface of the first HVW region into the first HVW region;
• a gate dielectric extending from over the first HVW region to over the second HVW region, wherein the gate dielectric has a portion over the insulation region;
• a gate electrode on the gate dielectric;
• a fourth HVW region of the second conductivity type overlying the substrate and laterally contacting the first HVW region, wherein the fourth HVW region is on an opposite side of the first HVW region relative to the second HVW region, and wherein the gate dielectric does not extend into the region directly over the fourth HVW region;
• and
• a fifth HVW region of the second conductivity type underlying the fourth HVW region, wherein the fifth HVW region does not extend into the region directly underlying the first HVW region, and wherein the fifth HVW region has a bottom substantially lower than the bottom of the first HVW region.