High-voltage MOS devices having gates extending into recesses of substrates

An integrated circuit structure comprising:

• a semiconductor substrate;
• a high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate;
• a first double diffusion (DD) region in the HVW region, the first DD region being of a second conductivity type opposite the first conductivity type;
• a second DD region of the second conductivity type in the HVW region, wherein the first DD region and the second DD region adjoin an intermediate portion of the HVW region between the first DD region and the second DD region;
• a recess extending from a top surface of the semiconductor substrate into the intermediate portion of the HVW region, wherein the recess comprises a first sidewall and a second sidewall opposing the first sidewall, and wherein the first sidewall is in the second DD region, and the second sidewall is in the intermediate portion of the HVW region;
• a gate dielectric continuously covering a first top surface of the first DD region and a second top surface of the second DD region, wherein the gate dielectric extends to a bottom of the recess;
• a gate electrode over the gate dielectric;
• a source region in the first DD region;
• and
• a drain region in the second DD region.

An integrated circuit structure comprising:

• a semiconductor substrate;
• a high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate;
• a first double diffusion (DD) region in the HVW region, the first DD region being of a second conductivity type opposite the first conductivity type;
• a second DD region of the second conductivity type in the HVW region, wherein the first DD region and the second DD region are spaced apart from each other;
• a gate dielectric over the HVW region, wherein the gate dielectric comprises a first portion lower than a first top surface of the first DD region and a second top surface of the second DD region, and wherein the first portion is between the first DD region and the second DD region;
• a gate electrode over the gate dielectric;
• a source region in the first DD region;
• and
• a drain region in the second DD region.