Semiconductor memory structures

A semiconductor structure, comprising:

• a transistor over a substrate, the transistor comprising a gate and a contact region adjacent to the gate and within the substrate;
• a first conductive layer over the contact region;
• a first dielectric layer over the first conductive layer;
• a second conductive layer within the first dielectric layer, contacting at least a portion of a top surface of the first conductive layer, the second conductive layer comprising a tapered cap portion extending above an uppermost surface of the first dielectric layer;
• at least one first dielectric spacer between the first dielectric layer and the second conductive layer;
• a phase change material layer above a top surface of the second conductive layer;
• a third conductive layer over the phase change material layer;
• a second dielectric layer formed over the first dielectric layer, such that the phase change material is separated from the first dielectric layer and the first dielectric spacer by the second dielectric layer;
• and
• at least one second dielectric spacer on a sidewall of the cap portion such that the tapered cap portion is completely separated from the second dielectric layer by the second dielectric spacer, wherein a thermal conductivity of the second dielectric spacer is less than a thermal conductivity of the first dielectric layer or a thermal conductivity of the second dielectric layer,
• wherein a top surface of the second dielectric spacer is substantially level with top surfaces of the tapered cap portion and the second dielectric layer.