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US 7,888,707 B2Granted
Gated diode nonvolatile memory process
AssigneeMacronix International Co., Ltd.
InventorsYi Ying Liao, Wen Jer Tsai, Chih Chieh Yeh
Life of this patent
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Abstract
A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
Claims26
An integrated circuit comprising:
- interlayer conductor interconnecting a plurality of arrays;
- the plurality of arrays in different layers separated by insulating layers, wherein each of said arrays comprises:
- a plurality of conducting lines connected to said interlayer conductor and accessing a plurality of cells arranged in rows and columns;
- and
- the plurality of cells arranged in rows and columns, wherein each of said cells comprises:
- a junction device including a junction;
- and
- a charge storage element sandwiched by said junction device and a corresponding conducting line of said plurality of conducting lines, wherein said junction device and said corresponding conducting line provide biases altering and sensing a state of said charge storage element, the charge storage element surrounding the junction device sufficiently to cover the junction of the junction device.
5 more elements
An integrated circuit comprising:
- an array comprising:
- a plurality of conducting lines, each connecting a row of a plurality of cells arranged in rows and columns;
- and
- the plurality of cells arranged in rows and columns, wherein each of said cells comprises:
- a junction device including a junction;
- a gate;
- and
- a charge storage element sandwiched by said junction device and a corresponding conducting line of said plurality of conducting lines, wherein said junction device and said corresponding conducting line provide biases altering and sensing a state of said charge storage element, the charge storage element surrounding the junction device sufficiently to cover the junction of the junction device.
5 more elements
An integrated circuit comprising:
- interlayer conductor interconnecting a plurality of arrays;
- and
- the plurality of arrays in different layers separated by insulating layers, wherein each of said arrays comprises:
- a plurality of wordlines;
- a plurality of bitlines interlacing said wordlines;
- and
- a plurality of cells deposited at intersections of said wordlines and bitlines, wherein each of said cells comprises:
- a junction device including a junction;
- and
- a charge storage element partly enclosing said junction device, the charge storage element sandwiched by said junction device and a corresponding wordline of said plurality of wordlines, wherein said junction device and said corresponding wordline provide biases altering and sensing a state of said charge storage element, the charge storage element surrounding the junction device sufficiently to cover the junction of the junction device.
7 more elements
An integrated circuit comprising:
- an array comprising:
- a plurality of wordlines;
- a plurality of bitlines interlacing said wordlines;
- and
- a plurality of cells deposited at intersections of said wordlines and bitlines, wherein each of said cells comprises:
- a junction device including a junction;
- and
- a charge storage element partly enclosing said junction device, the charge storage element sandwiched by said junction device and a corresponding wordline of said plurality of wordlines, wherein said junction device and said corresponding wordline provide biases altering and sensing a state of said charge storage element, the charge storage element surrounding the junction device sufficiently to cover the junction of the junction device.
5 more elements
Dependencies are inferred from the claim text.