Multilayer printed circuit board
AssigneeIbiden Co., Ltd.
InventorsHajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
Life of this patent
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Abstract
A multilayer printed circuit board has an IC chip included in a core substrate in advance, and an intermediate layer provided on a pad of the IC chip. Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the intermediate layer made of copper on the die pad, it is possible to prevent resin residues on the pad and to improve connection characteristics between the pad and a via hole, and to improve reliability.
Claims18
An IC chip device comprising:
- a semiconductor device;
- an electrode pad provided on the semiconductor device;
- a passivation layer formed on the semiconductor device and on a first portion of a surface of said electrode pad;
- and
- an intermediate layer formed directly on the electrode pad and on the passivation layer, the surface of the intermediate layer being larger than the surface of the electrode pad, and the intermediate layer comprising:
- a first metal layer formed directly on a second portion of the surface of said electrode pad where said passivation layer is not formed,
- a second metal layer formed directly on the first metal layer, and
- a third metal layer formed directly on the second metal layer,
- wherein, when the semiconductor device is accommodated in a printed circuit board, the intermediate layer establishes electrical connection between the electrode pad and a conductive circuit formed on a first interlayer insulating layer of the printed circuit board through a first via hole structure formed in the first interlayer insulating layer, the first via hole structure being electrically connected to a second via hole structure formed by a second interlayer insulating layer formed over the first interlayer insulating layer and the first via hole structure and having a second via hole opening therein and a second via hole structure formed in the second via hole opening.
An IC chip assembly comprising:
- a semiconductor device;
- an electrode pad provided on the semiconductor device;
- a passivation layer formed on the semiconductor device and on a first portion of a surface of said electrode pad;
- an intermediate layer formed directly on the electrode pad and on the passivation layer, the intermediate layer comprising:
- a first metal layer formed directly on a second portion of the surface of said electrode pad where said passivation layer is not formed,
- a second metal layer formed directly on the first metal layer, and
- a third metal layer formed directly on the second metal layer;
- a first insulating layer provided directly on the passivation layer and having a first via hole therein;
- a conductive circuit formed on the insulating layer;
- a first via conductor provided within said first via hole, the first via conductor being directly connected to at least a portion of the intermediate layer and directly connected to at least a portion of the conductive circuit formed on the insulating layer;
- a second insulating layer formed over the first insulating layer and the first via hole and having a second via hole therein;
- and
- a second via conductor provided within the second via hole opening of the second insulating layer and electrically connected to the first via hole structure.
Dependencies are inferred from the claim text.