US 7,888,252 B2Granted

Self-aligned contact

AssigneeInternational Business Machines Corporation

InventorsJohnathan E. Faltermeier, Stephan Grunow, Kangguo Cheng, Kevin Petrarca, Kaushik Kumar, Lawrence A. Clevenger, Shom Ponoth, Vidhya Ramachandran

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Abstract

A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

Claims18

Dependent claims

A method of forming self-aligned contacts, the method comprising the steps of:

providing a substrate including a plurality of gate stacks having a space between each of said plurality of gate stacks, said space exposing a contact adjacent said gate stacks;
conformally depositing a dielectric over said substrate so that dielectric divots are formed in the top surface of said dielectric over said space between said each of said plurality of gate stacks;
depositing a patterned masking layer over said dielectric layer, said patterned masking layer comprising openings aligned with and exposing said divots in said top surface of said dielectric, wherein said step of depositing a patterned masking layer comprises:
conformally depositing a random polymer layer within said dielectric divots, while leaving a top surface of said dielectric exposed over said gate stacks;
conformally depositing a multi-block self-assembly layer on said exposed dielectric and on said random polymer layer within said dielectric divots, so that each of said block materials self-organizes vertically within said dielectric divots;
etching one of said block materials selective to other of said block materials to form openings in said dielectric divots to expose said random polymer layer;
and
removing said random polymer layer through said openings so as to remove the remaining block materials from said dielectric divot to expose said dielectric within said dielectric divot, while leaving at least one layer of said block materials covering said dielectric over said gate stacks;
and
etching said dielectric through said openings to expose said contacts.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/372,174Filed 17 Feb 2009
Published: US 2010/0210098 A119 Aug 2010
Granted: 15 Feb 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10P 50/73
Etching of wafers, substrates or parts of devices: using masks for insulating materials
H10P 76/4085
Characterised by their sizes, orientations, dispositions, behaviours or shapes: characterised by the processes involved to create the masks
H10W 20/074
Of dielectric parts thereof: of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or…