Method of manufacturing an integrated circuit, an integrated circuit, and a memory module

A method of manufacturing an integrated circuit comprising a memory device, the method comprising:

• forming a solid electrolyte layer comprising a first solid electrolyte layer area and a second solid electrolyte layer area, a height of a top surface of the solid electrolyte layer within the second solid electrolyte layer area being lower than a height of a top surface of the solid electrolyte layer within the first solid electrolyte layer area, wherein the solid electrolyte layer comprises a solid electrolyte layer composite structure comprising a first solid electrolyte layer, a second solid electrolyte layer disposed above the first solid electrolyte layer, and an intermediate layer sandwiched between the first solid electrolyte layer and the second solid electrolyte layer;
• forming a conductive layer on or above the top surfaces of the first solid electrolyte layer area and the second solid electrolyte layer area;
• planarizing the top surface of the conductive layer such that the solid electrolyte layer is exposed within the first solid electrolyte layer area but is covered by the conductive layer within the second solid electrolyte layer area;
• and
• patterning the exposed solid electrolyte layer within the first solid electrolyte layer area.