US 7,888,214 B2Granted

Selective stress relaxation of contact etch stop layer through layout design

AssigneeGlobalfoundries Singapore Pte. Ltd.

InventorsLee Wee Teo, Elgin Quek, Dong Kyun Sohn

Life of this patent

Estimating the term…

Loading patent…

Abstract

A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.

Claims29

Dependent claims

A method of fabrication of a semiconductor device comprising:

providing a substrate having a PMOS region and a NMOS region;
providing a PMOS transistor in the PMOS region and a NMOS transistor in the NMOS region, wherein
the PMOS transistor comprises a PMOS gate, PMOS gate dielectric, PMOS channel and PMOS S/D regions, and
the NMOS transistor comprises a NMOS gate, NMOS gate dielectric, NMOS channel, and NMOS S/D regions;
forming a stress layer having a first stress over the substrate, the stress layer covering the PMOS region and the NMOS region;
forming a dielectric layer over the stress layer;
forming PMOS S/D contact holes having a PMOS S/D contact layout design through the stress layer in the PMOS region to expose portions of the PMOS S/D regions and NMOS S/D contact holes having a NMOS S/D contact layout design through the stress layer in the NMOS region to expose portions of the NMOS S/D regions, wherein
the PMOS S/D contact hole layout design is based on PMOS stress considerations and has a PMOS S/D contact hole area, the PMOS S/D contact layout design comprises adapting size, shape, number or location or a combination thereof of the PMOS S/D contact holes to cause the stress layer with the first stress to induce a first desired stress on the PMOS channel based on the PMOS stress considerations,
the NMOS S/D contact hole layout design is based on NMOS stress considerations and has a NMOS S/D contact hole area, and the NMOS S/D contact layout design comprises adapting size, shape, number or location or a combination thereof of the NMOS S/D contact holes to cause the stress layer with the first stress to induce a second desired stress on the NMOS channel based on the NMOS stress considerations,
wherein the PMOS S/D contact hole area is larger than the NMOS S/D contact hole area or the PMOS S/D contact holes are closer to the PMOS gate than the NMOS S/D contact holes are to the NMOS gate or a combination thereof, and
the first desired stress is different from the second desired stress;
and
forming contact plugs in the PMOS contact holes and the NMOS contact holes.

10 more elements

A semiconductor device comprising:

a substrate having a PMOS region and a NMOS region;
a PMOS transistor in the PMOS region and a NMOS transistor in the NMOS region,
wherein the PMOS transistor is comprised of a PMOS gate, PMOS gate dielectric, PMOS channel and PMOS S/D regions, and
the NMOS transistor is comprised of a NMOS gate, NMOS gate dielectric, NMOS channel, and NMOS S/D regions;
a stress layer having a first stress disposed over the substrate over the PMOS region and the NMOS region;
a dielectric layer disposed over the stress layer;
PMOS S/D contact holes having a PMOS S/D contact layout design through the stress layer in said PMOS region to expose portions of the PMOS S/D regions and NMOS S/D contact holes having a NMOS S/D contact layout design through the stress layer in the NMOS region to expose portions of the NMOS S/D regions,
wherein,
the PMOS S/D contact hole design is based on PMOS stress considerations and has a PMOS S/D contact hole area, the PMOS S/D contact layout design comprises adapting size, shape, number or location or a combination thereof of the PMOS S/D contact holes to cause the stress layer with the first stress to induce a first desired stress on the PMOS channel based on the PMOS stress considerations,
the NMOS S/D contact hole design is based on NMOS stress considerations and has a NMOS S/D contact hole area, the NMOS S/D contact layout design comprises adapting size, shape, number or location or a combination thereof of the NMOS S/D contact holes to cause the stress layer with the first stress to induce a second desired stress on the NMOS channel based on the NMOS stress considerations,
wherein the PMOS S/D contact hole area is larger than the NMOS S/D contact hole area or the PMOS S/D contact holes are closer to the PMOS gate than the NMOS S/D contact holes are to the NMOS gate or a combination thereof, and
the first desired stress is different from the second desired stress;
and
contact plugs in the PMOS contact holes and the NMOS contact holes.

11 more elements

A method of forming a device comprising:

providing a substrate prepared with first and second active regions, wherein the first active region comprises a first transistor and the second active region comprises a second transistor;
forming a stress layer having a first stress over the first and second active regions covering the first and second transistors;
forming a dielectric layer over the stress layer;
forming first and second contact openings in the first and second active regions in communication with diffusion regions of the first and second transistors, wherein
the first contact openings have a first contact layout design based on first stress considerations, the first contact layout design causes the stress layer with the first stress in the first active region to induce a first desired stress on a channel region of the first transistor based on the first stress considerations, the first contact openings of the first transistor comprise a first contact area, and
the second contact openings have a second contact layout design based on second stress considerations, the second contact layout design causes the stress layer with the first stress in the second active region to induce a second desired stress on a channel region of the second transistor based on the second stress considerations, the second contact openings of the second transistor comprise a second contact area, and
wherein the first contact area is smaller than the second contact area to reduce or minimize relaxing effects of the contact openings.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/302,035Filed 13 Dec 2005
Published: US 2007/0132032 A114 Jun 2007
Granted: 15 Feb 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels