Conductive channel pseudo block process and circuit to inhibit reverse engineering
AssigneeHRL Laboratories, LLC
InventorsLap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
Life of this patent
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Abstract
A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
Claims16
A method of making a semiconductor to make reverse engineering difficult comprising:
- forming on the semiconductor a first electrically conductive doped channel having a first doping type between at least two first active regions having the first doping type;
- forming a mask layer over a region between a first portion of said first electrically conductive doped channel and a second portion of said first electrically conductive doped channel;
- disposing a first conductive layer over the first portion of said first electrically conductive doped channel;
- disposing a second conductive layer over the second portion of said first electrically conductive doped channel wherein said first conductive layer and said second conductive layer are spaced apart from one another;
- forming on the semiconductor a second electrically conductive doped channel having a second doping type between at least two second active regions having the first doping type;
- forming the mask layer over a second region between a first portion of said second electrically conductive doped channel and a second portion of said second electrically conductive doped channel;
- disposing a third conductive layer over the first portion of said second electrically conductive doped channel;
- and
- disposing a fourth conductive layer over the second portion of said second electrically conductive doped channel wherein said third conductive layer and said fourth conductive layer are spaced apart from one another;
- wherein edges of the first and second conductive layers are in a same relative location as edges of the third and fourth conductive layers.
A method of making a semiconductor for protecting an integrated circuit design comprising:
- forming on the semiconductor first boundary edges of a first conductive layer by using a mask layer in first positions relative to a channel block having a first doping type to prevent the first conductive layer from forming an electrically conductive path over the channel block;
- and
- forming on the semiconductor second boundary edges of a second conductive layer by using the mask layer in second positions relative to a conducting channel having a second doping type, the second positions relative to the conducting channel being substantially similar to the first positions relative to the channel block.
A method of making a semiconductor for protecting an integrated circuit design comprising:
- forming on the semiconductor edges of a first conductive layer associated with a non-conducting channel-blocked channel by using a mask layer;
- and
- forming on the semiconductor edges of a second conductive layer associated with a pseudo channel-blocked conducting channel in the same disposition as said edges of said first conductive layer for said non-conducting channel-blocked channel by using the mask layer.
Dependencies are inferred from the claim text.