Highly scalable thin film transistor
AssigneeSanDisk 3D LLC
InventorsS. Brad Herner, Abhijit Bandyopadhyay
Life of this patent
Estimating the term…
Abstract
Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.
Claims14
A method for forming a monolithic three dimensional device, the method comprising:
- depositing a first semiconductor material layer above a substrate, wherein the first semiconductor material layer is amorphous as deposited and comprises silicon-germanium alloy;
- forming a first plurality of field effect transistors, each first field effect transistor having a first channel region comprising a portion of the first layer of semiconductor material;
- depositing a second semiconductor material layer above the first field effect transistors, wherein, when the second semiconductor material layer is deposited, the first layer of semiconductor material remains predominantly amorphous;
- and
- forming a second plurality of field effect transistors, each second field effect transistor having a second channel region comprising a portion of the second layer of semiconductor material;
- wherein:
- the step of forming the first plurality of field effect transistors comprises growing an oxide layer between the first channel region and a gate electrode of the first plurality of field effect transistors transistor, and depositing a high-k dielectric layer having a dielectric constant greater than 8 on and in contact with the oxide layer.
A method for forming a monolithic three dimensional device, the method comprising:
- depositing a first layer of semiconductor material above a substrate, wherein the first layer of semiconductor material is amorphous as deposited;
- forming a first plurality of field effect transistors, each first field effect transistor having a channel region comprising a portion of the first layer of semiconductor material;
- depositing a second layer of semiconductor material above the first field effect transistors, wherein, when the second layer of semiconductor material is deposited, the first layer of semiconductor material remains predominantly amorphous;
- forming a second plurality of field effect transistors, each second field effect transistor having a channel region comprising a portion of the second layer of semiconductor material;
- and
- recrystallizing the first and second layers of semiconductor material from amorphous form to polycrystalline form.
Dependencies are inferred from the claim text.